New patch to review for coreboot: 8bc71b8 northbridge/intel: Trivial fsp_rangeley northbridge cleanups
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6420
-gerrit
commit 8bc71b81a58392226ccc2141243be0fbcd61611c Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu Jul 31 09:07:38 2014 +1000
northbridge/intel: Trivial fsp_rangeley northbridge cleanups
Introduced in:
2963ae7 northbridge/intel: Add fsp_rangeley northbridge support
Change-Id: I13f2c46aa2bcedb9d1c66c485bf48ed7bc95d9c7 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/northbridge/intel/fsp_rangeley/chip.h | 2 +- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 6 ++---- src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 11 +++++------ 4 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 24609a1..0d19aa7 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -60,4 +60,4 @@ struct northbridge_intel_fsp_rangeley_config { uint8_t Bifurcation; };
-#endif +#endif /* _FSP_RANGELEY_CHIP_H_ */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..de60c5c 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -29,11 +29,9 @@ #include <fspvpd.h> #include <fspbootmode.h> #include <reset.h> -#include "../chip.h" - -#ifdef __PRE_RAM__ #include <southbridge/intel/fsp_rangeley/romstage.h> -#endif + +#include "../chip.h"
#ifdef __PRE_RAM__
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h index 3057865..845f9a2 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h @@ -42,7 +42,7 @@ }
/* - *The FSP Image ID is different for each platform's FSP and + * The FSP Image ID is different for each platform's FSP and * can be used to verify that the right FSP binary is loaded. * For the Rangeley FSP, the Image Id is "AVN-FSP0". */ diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 508630e..9dabd9f 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -18,17 +18,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif - -#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> +#include <stdint.h> + #include "northbridge.h"
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage + /* * Restricted Access Regions: *
-
Edward O'Callaghan