Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
nsekar@codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31142
Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ......................................................................
Qcs405: Add SPI chip select assert/de-assert in claim/release bus
Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions.
Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Signed-off-by: Prudhvi Yarlagadda pyarlaga@codeaurora.org Signed-off-by: Nitheesh Sekar nsekar@codeaurora.org --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31142/1
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ };
struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA);
- clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h>
static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; }
-static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; }
+ +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw;
/* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } }
+ stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw;
state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config;
+ /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config;
- /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } }
+ stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + }
cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret;
- write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ }
out: - write_force_cs(slave, 0);
/* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, };
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31142 )
Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ......................................................................
Patch Set 1:
(57 comments)
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c:
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@66 PS1, Line 66: { code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@66 PS1, Line 66: { please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@67 PS1, Line 67: .hz = 1000000, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@67 PS1, Line 67: .hz = 1000000, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@68 PS1, Line 68: .hw_ctl = 0x0, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@68 PS1, Line 68: .hw_ctl = 0x0, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@69 PS1, Line 69: .src = SRC_XO_19_2MHZ, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@69 PS1, Line 69: .src = SRC_XO_19_2MHZ, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@70 PS1, Line 70: .div = DIV(48), code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@70 PS1, Line 70: .div = DIV(48), please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@71 PS1, Line 71: //.m = 1, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@72 PS1, Line 72: //.n = 2, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@73 PS1, Line 73: //.d_2 = 4, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@73 PS1, Line 73: //.d_2 = 4, please, no space before tabs
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@73 PS1, Line 73: //.d_2 = 4, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@74 PS1, Line 74: }, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@74 PS1, Line 74: }, please, no space before tabs
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/clock.c@74 PS1, Line 74: }, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c:
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@341 PS1, Line 341: } void function return statements are not generally useful
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@352 PS1, Line 352: switch(slave->bus) { switch and case should be at the same indent
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@355 PS1, Line 355: GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@355 PS1, Line 355: GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@356 PS1, Line 356: gpio_configure(GPIO(38), 2, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@356 PS1, Line 356: gpio_configure(GPIO(38), 2, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@357 PS1, Line 357: GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@357 PS1, Line 357: GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@358 PS1, Line 358: gpio_configure(GPIO(117), 2, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@358 PS1, Line 358: gpio_configure(GPIO(117), 2, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@359 PS1, Line 359: GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@359 PS1, Line 359: GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@360 PS1, Line 360: gpio_configure(GPIO(118), 2, code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@360 PS1, Line 360: gpio_configure(GPIO(118), 2, please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@361 PS1, Line 361: GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out trailing whitespace
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@361 PS1, Line 361: GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@361 PS1, Line 361: GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@363 PS1, Line 363: break; trailing whitespace
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@364 PS1, Line 364: case 5: code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@364 PS1, Line 364: case 5: please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@366 PS1, Line 366: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@366 PS1, Line 366: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@366 PS1, Line 366: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@367 PS1, Line 367: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@367 PS1, Line 367: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@367 PS1, Line 367: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@368 PS1, Line 368: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@368 PS1, Line 368: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@368 PS1, Line 368: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@369 PS1, Line 369: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@369 PS1, Line 369: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); code indent should use tabs where possible
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@369 PS1, Line 369: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@524 PS1, Line 524: printk(BIOS_ERR, "SPI FIFO read timeout \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@529 PS1, Line 529: }while(!(val & MAX_INPUT_DONE_FLAG)); space required after that close brace '}'
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@529 PS1, Line 529: }while(!(val & MAX_INPUT_DONE_FLAG)); space required before the open parenthesis '('
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@651 PS1, Line 651: printk(BIOS_ERR, "SPI FIFO write timeout \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@656 PS1, Line 656: }while(!(val & MAX_OUTPUT_DONE_FLAG)); space required after that close brace '}'
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@656 PS1, Line 656: }while(!(val & MAX_OUTPUT_DONE_FLAG)); space required before the open parenthesis '('
https://review.coreboot.org/#/c/31142/1/src/soc/qualcomm/qcs405/spi.c@678 PS1, Line 678: printk(BIOS_ERR, "SPI:DBG write not success \n"); unnecessary whitespace before a quoted newline
nsekar@codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31142 )
Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ......................................................................
Abandoned
resolved by CB:32058 for SPI driver and CB:29962 for SPI Clock
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