Change in ...coreboot[master]: mb/google/hatch/variants/helios: Update Spd sources - coreboot-gerrit

2 Jul 2019


      Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 )
Change subject: mb/google/hatch/variants/helios: Update Spd sources
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Patch Set 1:
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Patch Set 1: Code-Review-1
(1 comment)
The DRAM ID table at Proto stage is
ID 0  Samsung 16Gb 2133MT/s K4E6E304EC/ED-EGCG
ID 1  Samsung 32Gb 2133MT/s K4EB304ED-EGCG
ID 2  Hynix    8Gb 2133MT/s H9CCNNN8GTALAR-NVD
ID 3  Hynix   16Gb 2133MT/s H9CCNNNBJTALAR-NVD
ID 4  Hynix   32Gb 2133MT/s H9CCNNNCLGALAR-NVD
According to Intel's feedback , current SPD support the same capacity and speed with different brand , so ID 0 and ID 3 use 1 SPD file . ID 1 and ID 4 use another SPD file .
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156
Gerrit-Change-Number: 33953
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