Change in ...coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753

Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................

src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI

Signed-off-by: Michał Żygowski 
Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
---
M src/soc/intel/fsp_baytrail/smm.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1

diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index 84f8d28..149272d 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -20,6 +20,7 @@
 #include <arch/io.h>
 #include <cpu/x86/smm.h>
 #include <string.h>
+#include <bootstate.h>

#include <soc/iomap.h>
 #include <soc/pmc.h>
@@ -124,3 +125,16 @@
    	  "d" (APM_CNT)
    );
 }
+
+static void finalize_chipset(void *unused)
+{
+	printk(BIOS_DEBUG, "Finalizing SMM.\n");
+	/* Lock sleep stretching policy and set SMI lock. */
+	write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2),
+		read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2))
+		| SLPSX_STR_POL_LOCK | SMI_LOCK);
+	outb(APM_CNT_FINALIZE, APM_CNT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);

[Michał Żygowski (Code Review)]

Hello Patrick Rudolph, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/30753

to look at the new patch set (#2).

Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................

src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI

Signed-off-by: Michał Żygowski 
Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
---
M src/soc/intel/fsp_baytrail/smm.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/2

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30753 )

Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30753 )

Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................

src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI

Signed-off-by: Michał Żygowski 
Change-Id: Ia296a680217a38136c063cae6ed619df0c497795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30753
Reviewed-by: Philipp Deppenwiese 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/fsp_baytrail/smm.c
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Philipp Deppenwiese: Looks good to me, approved

diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index 94b0944..df55433 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -20,6 +20,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <cpu/x86/smm.h>
+#include <bootstate.h>
 #include <soc/iomap.h>
 #include <soc/pmc.h>
 #include <soc/smm.h>
@@ -123,3 +124,16 @@
    	  "d" (APM_CNT)
    );
 }
+
+static void finalize_chipset(void *unused)
+{
+	printk(BIOS_DEBUG, "Finalizing SMM.\n");
+	/* Lock sleep stretching policy and set SMI lock. */
+	write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2),
+		read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2))
+		| SLPSX_STR_POL_LOCK | SMI_LOCK);
+	outb(APM_CNT_FINALIZE, APM_CNT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);

Change in coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30753 )

Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/30753/3/src/soc/intel/fsp_baytrail/... 
File src/soc/intel/fsp_baytrail/smm.c:

https://review.coreboot.org/c/coreboot/+/30753/3/src/soc/intel/fsp_baytrail/... 
PS3, Line 135: APM_CNT_FINALIZE
This is not handled in the smihandler? Why is it added?