Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753
Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI ......................................................................
src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 --- M src/soc/intel/fsp_baytrail/smm.c 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 84f8d28..149272d 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <string.h> +#include <bootstate.h>
#include <soc/iomap.h> #include <soc/pmc.h> @@ -124,3 +125,16 @@ "d" (APM_CNT) ); } + +static void finalize_chipset(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + /* Lock sleep stretching policy and set SMI lock. */ + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), + read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) + | SLPSX_STR_POL_LOCK | SMI_LOCK); + outb(APM_CNT_FINALIZE, APM_CNT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);