Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
mb/google/volteer: use the new generic SPDs
Switch to using SPD file SPD_LPDDR4X_200b_1R_16Gb_4267 for part number K4U6E3S4AA-MGCL.
Switch to using SPD file SPD_LPDDR4X_200b_2R_32Gb_4266 for part number K4UBE3D4AA-MGCR.
Remove SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex and SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex as they're no longer needed.
BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flashed and booted a ripto and a volteer SKU4 successfully to the kernel.
Change-Id: I3608968ce62c615645941d8e141a8df4cb9b41a8 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/variants/malefor/Makefile.inc M src/mainboard/google/volteer/variants/ripto/Makefile.inc M src/mainboard/google/volteer/variants/volteer/Makefile.inc 5 files changed, 4 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40540/1
diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex deleted file mode 100644 index 94f258e..0000000 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00 -48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex deleted file mode 100644 index 90202f9..0000000 --- a/src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00 -48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/malefor/Makefile.inc b/src/mainboard/google/volteer/variants/malefor/Makefile.inc index 8a7cbec..2c96e39 100644 --- a/src/mainboard/google/volteer/variants/malefor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/malefor/Makefile.inc @@ -2,7 +2,7 @@ ## This file is part of the coreboot project.
## Memory Options -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 +SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000
romstage-y += memory.c
diff --git a/src/mainboard/google/volteer/variants/ripto/Makefile.inc b/src/mainboard/google/volteer/variants/ripto/Makefile.inc index ebfdbd5..1e156a8 100644 --- a/src/mainboard/google/volteer/variants/ripto/Makefile.inc +++ b/src/mainboard/google/volteer/variants/ripto/Makefile.inc @@ -12,7 +12,7 @@ ## GNU General Public License for more details. ##
-SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 +SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000
bootblock-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc index 3c3eba0..ae0275d 100644 --- a/src/mainboard/google/volteer/variants/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -6,5 +6,5 @@ ##
## Memory Options -SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 -SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 +SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000 +SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4266 # 0b0001
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 4:
ping...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP Was the DDP changed to QDP on purpose?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Was the DDP changed to QDP on purpose?
Yes. Intel did not release a DDP for this category (see https://b.corp.google.com/issues/148182234#comment22)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Yes. Intel did not release a DDP for this category (see https://b.corp.google. […]
Are you capturing all these details in some doc? It is going to be very confusing especially for partners if we are not consistent about the naming. I understand that these might be the names that Intel provided to the generic SPDs they shared, but can these be named consistently to ensure that there is no confusion?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Are you capturing all these details in some doc? It is going to be very confusing especially for par […]
If you feel the naming is more important than staying in sync with Intel released SPDs, I can rename SPD_LPDDR4X_200b_2R_32Gb_QDP_4266 to SPD_LPDDR4X_200b_2R_32Gb_DDP_4267. In the Volteer DRAM ID document, there's a paragraph on how to select a generic SPD for the desired memory part. That method doesn't currently use the generic SPD filename as part of the process when determining which generic SPD to use, but it would be nice to get to a point where an SPD wasn't required from the memory vendor as long as the ODM can determine the characteristics we care about. Not sure we could ever reliably get there as even memory vendors seems to misunderstand some of the SPD categories (QDP vs. DDP as mentioned in that bug, for example).
re: "can these be named consistently to ensure that there is no confusion"
I think for truly consistent naming given Intel's generic SPDs, we would need to extend the filename to also include categories for CAS latencies supported, SDRAM Minimum Cycle Time and SDRAM Max Cycle Time.
If you think it will reduce confusion to add these categories to the filename, I can do that.
Should I add these categories to the naming?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
If you feel the naming is more important than staying in sync with Intel released SPDs, I can rename […]
I don't think this is correct. SPD information is tied to a set of characteristics that you have identified -- rank, speed grade, capacity, etc. Rest of the parameters should really be dependent on those attributes and we do not need to encode CAS, etc. differently. What a memory vendor provides is from the perspective of a DIMM, but we are using memory down configuration which is kind of simulating a DIMM. So, yes the values provided by memory part vendor might need to be massaged to make them work for the memory down case.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
I don't think this is correct. […]
re: " and we do not need to encode CAS"
Not sure I understand. Different modules have different CAS latencies, and Intel has specified byte offsets 21, 22, and 24 (CAS latencies supported) to be relevant fields that the MRC code uses.
Are you suggesting that we change those fields from what the vendor has specified for their part, trying to find a common setting that works for all? That doesn't sound feasible to me without having a working sample of each possible memory module to experiment with. I could guess at common timing settings, but if we guess and are wrong, it could cause issues for a factory build.
I added row count and CAS to the filename scheme. I think that may be sufficient to cover all known cases without having to fudge speed to come up with a unique filename (eg. SPD_LPDDR4X_200b_16row_2R_32Gb_540587cas_QDP_4267.spd.hex & SPD_LPDDR4X_200b_16row_2R_32Gb_55008Ccas_QDP_4267.spd.hex).
Let me know what route you want us to take here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Different modules have different CAS latencies,
In my understanding, those CAS latencies are derived based on some other attributes of the memory part. Have we really identified those set of attributes?
Are you suggesting that we change those fields from what the vendor has specified for their part, trying to find a common setting that works for all? That doesn't sound feasible to me without having a working sample of each possible memory module to experiment with. I could guess at common timing settings, but if we guess and are wrong, it could cause issues for a factory build.
I am not saying that we should just guess the values. If there are differences, we should talk to Intel about that to understand why those differences are present and what are the prime attributes that those rely on. Else, we will never be able to come up with true generic SPDs.
Let me know what route you want us to take here.
I think the first step should be to identify what memory characteristics matter in differentiating any given memory part.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Different modules have different CAS latencies, […]
re: "I think the first step should be to identify what memory characteristics matter in differentiating any given memory part."
We need to first define level of differentiation. The current generic SPDs from Intel is their crack at pruning down the non-essentials, leaving only the differentiable settings the MRC needs. The levels I see would be : 1) part wouldn't work if set incorrectly (eg. rank) 2) part might work if setting not exact for part but may be unreliable (eg. timing settings) 3) part functionality would see no difference (eg. vendor ID)
The generic SPDs that Intel released that are in this CL stripped out category 3, and represent Intel's belief for what is minimally necessary. I will push to see if we can play around with category 2 fields to try to reduce the collection of generic SPDs further, and will file a bug against Intel to start having this discussion.
For the record, I am concerned about flakey DRAM bugs that we may encounter if memory parts aren't being run with their vendor specified timings, and don't feel that risk is worth saving the space of a few additional SPD files in the sourcetree.
I will play around with CAS timings in the SPD that my SKU4 is using to get a better understanding for how picky these parts may or may not be about their timing settings. Perhaps my concern there is unwarranted and lpddr4x is not that sensitive.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
For the record, I am concerned about flakey DRAM bugs that we may encounter if memory parts aren't being run with their vendor specified timings, and don't feel that risk is worth saving the space of a few additional SPD files in the sourcetree.
It is not just about saving a few additional SPD files in sourcetree. Having these different categories is going to make it even more challenging as we add new memory parts. We need to have a very clear understanding of what attributes of the memory part really matter for the MRC. Remember that we are simulating DIMMs using memory down configuration. So, it is not necessary that whatever the vendor is providing is to be used exactly. We need to understand how MRC really utilizes these values. Based on that, we can come up with very clear recommendations on how a new memory part can be put into the right bucket. Feel free to raise questions and ask for more clarification from Intel if you are not sure about any of these bytes or what really causes them to be different than other parts of similar memory attributes.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
For the record, I am concerned about flakey DRAM bugs that we may encounter if memory parts aren't […]
How about adding a comment on each generic SPD with the specific DDR chips that it supports, or has been tested with?
Hello Jes Klinke, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Caveh Jalali, Duncan Laurie,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40540
to look at the new patch set (#9).
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
mb/google/volteer: use the new generic SPDs
Switch to using SPD file SPD_LPDDR4X_200b_1R_16Gb_4267.spd.hex for part number K4U6E3S4AA-MGCL.
Switch to using SPD_LPDDR4X_200b_2R_32Gb_87MinCAS_QDP_4267.spd.hex for part number K4UBE3D4AA-MGCR.
Remove SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex and SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex as they're no longer needed.
BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flashed and booted a ripto and a volteer SKU4 successfully to the kernel.
Change-Id: I3608968ce62c615645941d8e141a8df4cb9b41a8 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/variants/malefor/Makefile.inc M src/mainboard/google/volteer/variants/ripto/Makefile.inc M src/mainboard/google/volteer/variants/volteer/Makefile.inc 5 files changed, 4 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40540/9
Hello Jes Klinke, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Caveh Jalali, Duncan Laurie,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40540
to look at the new patch set (#11).
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
mb/google/volteer: use the new generic SPDs
Switch to using SPD file SPD_LPDDR4X_200b_1R_16Gb_4267.spd.hex for part number K4U6E3S4AA-MGCL.
Switch to using SPD_LPDDR4X_200b_2R_32Gb_87MinCAS_QDP_4267.spd.hex for part number K4UBE3D4AA-MGCR.
Remove SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex and SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex as they're no longer needed.
BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flashed and booted a ripto and a volteer SKU4 successfully to the kernel.
Change-Id: I3608968ce62c615645941d8e141a8df4cb9b41a8 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex D src/mainboard/google/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex M src/mainboard/google/volteer/variants/malefor/Makefile.inc M src/mainboard/google/volteer/variants/ripto/Makefile.inc M src/mainboard/google/volteer/variants/volteer/Makefile.inc 5 files changed, 7 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40540/11
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
How about adding a comment on each generic SPD with the specific DDR chips that it supports, or has […]
Done
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 11: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Done
Angel, that's a good suggestion, but there's not a way to encapsulate that information in the file itself. I'm creating a document that tracks that information, perhaps I should check something similar into mainboard/google/volteer/spd/ that contains this information.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 12: Code-Review-2
Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Abandoned
Changing direction, abandoned for 41184
-
Angel Pons (Code Review) -
Duncan Laurie (Code Review)
-
Furquan Shaikh (Code Review)
-
Nick Vaccaro (Code Review)