Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
Are you capturing all these details in some doc? It is going to be very confusing especially for par […]
If you feel the naming is more important than staying in sync with Intel released SPDs, I can rename SPD_LPDDR4X_200b_2R_32Gb_QDP_4266 to SPD_LPDDR4X_200b_2R_32Gb_DDP_4267. In the Volteer DRAM ID document, there's a paragraph on how to select a generic SPD for the desired memory part. That method doesn't currently use the generic SPD filename as part of the process when determining which generic SPD to use, but it would be nice to get to a point where an SPD wasn't required from the memory vendor as long as the ODM can determine the characteristics we care about. Not sure we could ever reliably get there as even memory vendors seems to misunderstand some of the SPD categories (QDP vs. DDP as mentioned in that bug, for example).
re: "can these be named consistently to ensure that there is no confusion"
I think for truly consistent naming given Intel's generic SPDs, we would need to extend the filename to also include categories for CAS latencies supported, SDRAM Minimum Cycle Time and SDRAM Max Cycle Time.
If you think it will reduce confusion to add these categories to the filename, I can do that.
Should I add these categories to the naming?