Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40540 )
Change subject: mb/google/volteer: use the new generic SPDs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/volteer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/40540/5/src/mainboard/google/voltee... PS5, Line 10: QDP
For the record, I am concerned about flakey DRAM bugs that we may encounter if memory parts aren't being run with their vendor specified timings, and don't feel that risk is worth saving the space of a few additional SPD files in the sourcetree.
It is not just about saving a few additional SPD files in sourcetree. Having these different categories is going to make it even more challenging as we add new memory parts. We need to have a very clear understanding of what attributes of the memory part really matter for the MRC. Remember that we are simulating DIMMs using memory down configuration. So, it is not necessary that whatever the vendor is providing is to be used exactly. We need to understand how MRC really utilizes these values. Based on that, we can come up with very clear recommendations on how a new memory part can be put into the right bucket. Feel free to raise questions and ask for more clarification from Intel if you are not sure about any of these bytes or what really causes them to be different than other parts of similar memory attributes.