[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8:
> So currently they are switched.

its kind of miss i believe when initial code been developed.

basically one need to tell the C-state capability when S0ix is enable/disable.