[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8: 
  So currently they are switched.
its kind of miss
i believe when initial code been developed.

basically one need to tell the C-state capability when S0ix is enable/disable.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Gerrit-Change-Number: 31153
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
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Gerrit-Comment-Date: Thu, 31 Jan 2019 10:57:49 +0000
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