[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Aamir Bohra, Ronak Kanabar, Paul Menzel, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31153

to look at the new patch set (#2).

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
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soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
> > iasl -d SSDT # to generate SSDT.dsl

Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik 
---
M src/soc/intel/icelake/acpi.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31153/2