Attention is currently required from: Paul Menzel, Iru Cai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46832 )
Change subject: autoport: Add Broadwell SoC support ......................................................................
Patch Set 9:
(4 comments)
File util/autoport/wildcatpoint.go:
https://review.coreboot.org/c/coreboot/+/46832/comment/c6b44125_72beaadf PS9, Line 43: if bdw.variant == CORE_M { : nPorts = 10 : } else { : nPorts = 8 : } Where does this information come from?
https://review.coreboot.org/c/coreboot/+/46832/comment/7aa3940b_0360f600 PS9, Line 148: /* FIXME: check these values */ : pei_data->dimm_channel0_disabled = 0; : pei_data->dimm_channel1_disabled = 0; : pei_data->spd_addresses[0] = 0xa0; : pei_data->spd_addresses[1] = 0xa2; : pei_data->spd_addresses[2] = 0xa4; : pei_data->spd_addresses[3] = 0xa6; Broadwell ULT/ULX only supports 1 DIMM per channel. I'd just write:
/* FIXME: check these values */ pei_data->dimm_channel0_disabled = 2; pei_data->dimm_channel1_disabled = 2; pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4;
https://review.coreboot.org/c/coreboot/+/46832/comment/6235ac60_edd5452e PS9, Line 237: "pcie_port_coalesce": "1", Why enabled by default?
https://review.coreboot.org/c/coreboot/+/46832/comment/42609ea6_6bd7b1d1 PS9, Line 287: Split from soc/intel/broadwell/acpi/platform.asl Why?