8 Jan
2021
8 Jan
'21
12:27 a.m.
Attention is currently required from: Nico Huber. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49184 )
Change subject: mb/asrock/h110m: Fix HECI state in devicetree ......................................................................
Patch Set 5: Code-Review-1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49184/comment/375991d4_ba90857c PS3, Line 9: making its state equal with the HeciEnabled : option
Should we? It depends on the point in coreboot when `HeciEnabled` […]
Just looked it after. It happens while `soc_finalize()`, after PCI enumeration. I thought `HeciEnabled` would set a FSP UPD. So I will leave it as it is.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I67a9f0a66bcc51c6153a76bfaaebdf1e7f07d55d
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