Samuel Holland has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44696 )
Change subject: mb/intel/dq45ek: Add new mainboard ......................................................................
Patch Set 2:
(3 comments)
I had this change marked WIP, so I could finish the IRQ routing and look at the ACPI tables and maybe C-states. But apparently I can't respond to comments unless I remove the WIP flag.
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@13 PS1, Line 13: GPIO33
Where is it?
On the back of the board, underneath the ICH10. I marked it, but I forgot to take a photo before putting the board in a rather cramped case. I was planning to write up a documentation page with a picture, so I only put the notes here temporarily.
https://review.coreboot.org/c/coreboot/+/44696/1//COMMIT_MSG@17 PS1, Line 17: fan control
This board uses Intel Quiet System Technology, which means the ME does fan control. It's expected. […]
Both fans are affected, as both are driven by the PCH. The SuperIO has no fan control.
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... File src/mainboard/intel/dq45ek/gpio.c:
https://review.coreboot.org/c/coreboot/+/44696/1/src/mainboard/intel/dq45ek/... PS1, Line 88: static const struct pch_gpio_set3 pch_gpio_set3_mode = { : .gpio72 = GPIO_MODE_GPIO, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_direction = { : .gpio72 = GPIO_DIR_INPUT, : }; : : static const struct pch_gpio_set3 pch_gpio_set3_level = { };
Do these exist on ICH10?
GPIO72 is described in section 13.10.12 of the datasheet. The values are copied from inteltool output.