Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37996 )
Change subject: soc/mediatek/mt8183: do TX tracking for DRAM DVFS feature ......................................................................
Patch Set 12:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37996/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37996/12//COMMIT_MSG@13 PS12, Line 13: b:none b:142358843
https://review.coreboot.org/c/coreboot/+/37996/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/37996/9/src/soc/mediatek/mt8183/dra... PS9, Line 2142: return;
the DDR not response to the DRAM controler, the error result undefined!
Ack
https://review.coreboot.org/c/coreboot/+/37996/9/src/soc/mediatek/mt8183/dra... PS9, Line 2214: void dramc_hw_dqsosc(u8 chn)
most of this is accomplished by the DRAM control hardware, no need detail description.
Ack
https://review.coreboot.org/c/coreboot/+/37996/9/src/soc/mediatek/mt8183/dra... PS9, Line 2316: return ((n < 0) ^ (d < 0)) ? ((n - d/2)/d) : ((n + d/2)/d);
use DIV_ROUND_CLOSEST replace this API.remove this API later.
Ack
https://review.coreboot.org/c/coreboot/+/37996/12/src/soc/mediatek/mt8183/dr... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/37996/12/src/soc/mediatek/mt8183/dr... PS12, Line 122: 0x%x %#x
https://review.coreboot.org/c/coreboot/+/37996/12/src/soc/mediatek/mt8183/dr... PS12, Line 2181: 0x%X %#x