[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Increase dcache size

[Shelley Chen (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Julius Werner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45827

to look at the new patch set (#2).

Change subject: soc/intel/braswell: Increase dcache size
......................................................................

soc/intel/braswell: Increase dcache size

Increase the DRAM cache size for Braswell to address the
compilation error

Cache as RAM area too full

when moving the mrc_cache writeback to romstage.  We need to increase
this first before landing the CL moving mrc_cache writeback to
romstage.

BUG=b:150502246
BRANCH=None
TEST=Able to successfully compile braswell boards

Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen 
---
M src/soc/intel/braswell/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/2