[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................

Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8: 
So currently they are switched.

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@9 
PS1, Line 9: TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Having the actual commands to do that would be helpful.