[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. (
https://review.coreboot.org/c/coreboot/+/31153 )

Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix
......................................................................


Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 
PS1, Line 8: 
So currently they are switched.


https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@9 
PS1, Line 9: TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Having the actual commands to do that would be helpful.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Gerrit-Change-Number: 31153
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
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Gerrit-Comment-Date: Thu, 31 Jan 2019 10:47:15 +0000
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