Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31153 ) Change subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/31153/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@8 PS1, Line 8: So currently they are switched. https://review.coreboot.org/#/c/31153/1//COMMIT_MSG@9 PS1, Line 9: TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. Having the actual commands to do that would be helpful. -- To view, visit https://review.coreboot.org/c/coreboot/+/31153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Gerrit-Change-Number: 31153 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar@intel.com> Gerrit-Reviewer: Shelley Chen <shchen@google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Thu, 31 Jan 2019 10:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment