coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Enable early EC software sync for Rull
by Pranava Y N (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87104?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Jayvik Desai Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull ...................................................................... mb/google/nissa/var/rull: Enable early EC software sync for Rull Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software sync in romstage. This is useful to achieve full USB-PD negotiation early in the boot flow. It eliminates a problem seen in rull devices where PMC is wrongly configured in depthcharge during the EC-sync scenario which prevents USB devices from getting detected when connected via a self-powered USB hub. BUG=b:386920751 TEST=Verify detection and booting to OS from USB drive connected to the Servo v4 debugger (self-powered hub) during the EC-sync scenario. Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/87104/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Gerrit-Change-Number: 87104 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Enable early EC software sync for Rull
by Jayvik Desai (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/87104?usp=email ) Change subject: mb/google/brya: Enable early EC software sync for Rull ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f Gerrit-Change-Number: 87104 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 02 Apr 2025 13:25:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: security/tpm: Add TPM2 NV_ReadPublic command support
by Filip Lewiński (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Julius Werner, Krystian Hebel, Martin Roth, Matt DeVillier, Michał Kopeć, Michał Żygowski. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82037?usp=email ) Change subject: security/tpm: Add TPM2 NV_ReadPublic command support ...................................................................... Patch Set 28: (2 comments) This change is ready for review. File src/security/tpm/tss/tcg-2.0/tss.c: https://review.coreboot.org/c/coreboot/+/82037/comment/95b5a580_6de47ea1?us… : PS16, Line 395: struct nv_read_public_response *nvrp_resp > These TPM spec specific structures are usually only for use inside the TSS layer, and we prefer to u […] @jwerner@chromium.org I've [refactored](https://review.coreboot.org/c/coreboot/+/82037/28/src/security/… the function and its uses to work on separate pointers. File src/security/tpm/tss/tcg-2.0/tss_structures.h: https://review.coreboot.org/c/coreboot/+/82037/comment/fad6140c_6c4d671d?us… : PS16, Line 330: uint8_t sha512[SHA512_DIGEST_SIZE]; > I don't really understand why this digest is inline in the union while in all other cases we use a p […] @jwerner@chromium.org Hmmm, yes, you are right that this structure differs from others that use pointers to external buffers. However in this case, the use of inline arrays in TPMU_HA (and by extension TPMT_HA, TPML_DIGEST_VALUES, and TPMU_NAME) actually follows the TPM 2.0 Library Spec — specifically, Table 71 and Table 72 in Part 2: Structures. The spec defines the union members as fixed-size arrays, and hashAlg serves as the selector for which one is valid. I agree it might make sense to unify how digests are handled throughout the codebase, especially if we're aiming for a consistent pointer-based model. That said, this feels like a broader refactor that probably deserves its own dedicated patch, since it's a bit outside the scope of the changes here (which are focused on NV_ReadPublic support). -- To view, visit https://review.coreboot.org/c/coreboot/+/82037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c032b4f88d445372beebbe354f458a061a63bb9 Gerrit-Change-Number: 82037 Gerrit-PatchSet: 28 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Apr 2025 13:15:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: drivers/smmstore: Support 64-bit MMIO addresses
by Patrick Rudolph (Code Review) 02 Apr '25

02 Apr '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87114?usp=email ) Change subject: drivers/smmstore: Support 64-bit MMIO addresses ...................................................................... drivers/smmstore: Support 64-bit MMIO addresses Currently the SMMSTOREv2 only support MMIO ROM below 4GiB. As the space below 4GiB is typically limited on x86, add support for extended MMIO ROM windows as found on recent hardware. Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new field to the coreboot table called 'mmap_addr_high'. The users outside of coreboot must check the size field of the coreboot struct to determine if mmap_addr_high is supported. When it is it holds the 64-bit physical address to the MMIO ROM window. Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/drivers/smmstorev2.md M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/smmstore/ramstage.c M src/include/smmstore.h 4 files changed, 25 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/87114/1 diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index af6e0ce..2e9f38f 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -74,19 +74,26 @@ struct lb_smmstorev2 { uint32_t tag; uint32_t size; - uint32_t num_blocks; /* Number of writeable blocks in SMM */ - uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ - uint32_t mmap_addr; /* MMIO address of the store for read only access */ - uint32_t com_buffer; /* Physical address of the communication buffer */ - uint32_t com_buffer_size; /* Size of the communication buffer in byte */ - uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ - uint8_t unused[3]; /* Set to zero */ + uint32_t num_blocks; /* Number of writable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access. + When set to zero the address is set in mmap_addr_high. */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ + uint64_t mmap_addr_high; /* When the ROM MMIO address is above 4GiB the 'mmap_addr' cannot hold it. + In that case 'mmap_addr' is cleared and the address to the ROM MMIO is + passed here. (Optional) */ }; ``` The absence of this coreboot table entry indicates that there's no SMMSTOREv2 support. +`mmap_addr_high` is an optional field added after the initial implementation. +Users of this table must check the size field to know if it's written by coreboot. +In case it's not present the SPI ROM MMIO address must be below 4 GiB. ### Blocks The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 78dbe8e..c0cfa39 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -539,11 +539,15 @@ uint32_t size; uint32_t num_blocks; /* Number of writable blocks in SMM */ uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ - uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t mmap_addr; /* MMIO address of the store for read only access. + When set to zero the address is set in mmap_addr_high. */ uint32_t com_buffer; /* Physical address of the communication buffer */ uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ uint8_t unused[3]; /* Set to zero */ + uint64_t mmap_addr_high; /* When the ROM MMIO address is above 4GiB the 'mmap_addr' cannot hold it. + In that case 'mmap_addr' is cleared and the address to the ROM MMIO is + passed here. (Added after initial implementation) */ }; enum lb_tpm_ppi_tpm_version { diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index 1cbf9fb..85dfff2 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -28,7 +28,11 @@ store->size = sizeof(*store); store->com_buffer = (uintptr_t)cbmem_entry_start(e); store->com_buffer_size = cbmem_entry_size(e); - store->mmap_addr = info.mmap_addr; + if (info.mmap_addr < 4ULL * GiB) + store->mmap_addr = info.mmap_addr; + else + store->mmap_addr = 0; + store->mmap_addr_high = info.mmap_addr; store->num_blocks = info.num_blocks; store->block_size = info.block_size; store->apm_cmd = APM_CNT_SMMSTORE; diff --git a/src/include/smmstore.h b/src/include/smmstore.h index 6805cbc..ef7bd1f 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -59,7 +59,7 @@ struct smmstore_params_info { uint32_t num_blocks; uint32_t block_size; - uint32_t mmap_addr; + uint64_t mmap_addr; } __packed; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/87114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7 Gerrit-Change-Number: 87114 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Enable HDA SDI based on FW config
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87090?usp=email to look at the new patch set (#4). Change subject: mb/google/fatcat: Enable HDA SDI based on FW config ...................................................................... mb/google/fatcat: Enable HDA SDI based on FW config This commit modifies the handling of PCH High Definition Audio (HDA) Serial Digital Interface (SDI) enablement. - In `devicetree.cb`, the static `pch_hda_sdi_enable` property is removed to allow varaints to override if needed. - In `variant.c`, `variant_update_soc_memory_init_params` is introduced to dynamically configure `PchHdaSdiEnable` UPD based on the firmware configuration (for example: `AUDIO_ALC256_HDA` or `AUDIO_ALC256M_CG_HDA`). SDI is enabled if this FW config option is present. Otherwise, it defaults to disabled. - `variant.c` is now added for romstage as well because the SDI configuration needs to happen earlier in the boot process. BUG=b:328770565, b:407876136 TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio. Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk M src/mainboard/google/fatcat/variants/fatcat/variant.c M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/variant.c 5 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/87090/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5 Gerrit-Change-Number: 87090 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Directly assign HDA SDI enable
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87109?usp=email ) Change subject: soc/intel/pantherlake: Directly assign HDA SDI enable ...................................................................... soc/intel/pantherlake: Directly assign HDA SDI enable The double negation (`!!`) was unnecessarily used when assigning the `pch_hda_sdi_enable` type boolean from the SOC config to the FSP M config. This commit removes the redundant `!!` operator, directly assigning the boolean value of `config->pch_hda_sdi_enable[i]` to `m_cfg->PchHdaSdiEnable[i]`. TEST=Able to build and boot google/fatcat. Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/87109/1 diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b5fc93b..521d2f2 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -162,7 +162,7 @@ m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) - m_cfg->PchHdaSdiEnable[i] = !!config->pch_hda_sdi_enable[i]; + m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/87109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9233116ca2bfaeac2f685d464a1cb261f067db6a Gerrit-Change-Number: 87109 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Increase CBFS mcache size
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87108?usp=email ) Change subject: soc/intel/pantherlake: Increase CBFS mcache size ...................................................................... soc/intel/pantherlake: Increase CBFS mcache size This patch overrides `CONFIG_CBFS_MCACHE_SIZE` Kconfig option with updated size of the CBFS memory cache to 0x8000 bytes. TEST=Able to build and boot google/fatcat w/o any error. w/o this patch: ``` [ERROR] CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size! ``` Change-Id: Ib6f046c7211a020c15d89a02348ea89f095273ed Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/87108/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index d372a6f..a884631 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -319,6 +319,10 @@ hex default 0x200000 +config CBFS_MCACHE_SIZE + hex + default 0x8000 + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x2000 -- To view, visit https://review.coreboot.org/c/coreboot/+/87108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6f046c7211a020c15d89a02348ea89f095273ed Gerrit-Change-Number: 87108 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Enable HDA SDI based on FW config
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87090?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Enable HDA SDI based on FW config ...................................................................... mb/google/fatcat: Enable HDA SDI based on FW config This commit modifies the handling of PCH High Definition Audio (HDA) Serial Digital Interface (SDI) enablement. - In `devicetree.cb`, the static `pch_hda_sdi_enable` property is removed to allow varaints to override if needed. - In `variant.c`, `variant_update_soc_memory_init_params` is introduced to dynamically configure `PchHdaSdiEnable` UPD based on the firmware configuration (for example: `AUDIO_ALC256_HDA` or `AUDIO_ALC256M_CG_HDA`). SDI is enabled if this FW config option is present. Otherwise, it defaults to disabled. - `variant.c` is now added for romstage as well because the SDI configuration needs to happen earlier in the boot process. BUG=b:328770565, b:407876136 TEST=Able to reduce the boot time by 18ms for SKUs w/o HDA audio. Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk M src/mainboard/google/fatcat/variants/fatcat/variant.c M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/variant.c 5 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/87090/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice28ea7445a5cb32fe8263ada363d4f45c3152f5 Gerrit-Change-Number: 87090 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Allow board-specific FSP-M UPD override
by Subrata Banik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Sowmya Aralguppe. Hello Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87089?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override ...................................................................... mb/google/fatcat: Allow board-specific FSP-M UPD override This commit introduces a mechanism to allow mainboards to override the default FSP-M UPDs for Panther Lake. - Adds `variant_update_soc_memory_init_params` as a weak function in `variants.h` and `romstage.c` for board-specific implementations. - In `romstage.c`, `mainboard_memory_init_params` now calls `variant_update_soc_memory_init_params` to apply board-specific overrides to the FSP-M UPDs. This enables finer-grained control over memory initialization parameters at the variant level. BUG=b:328770565 TEST=Able to reduce the boot time by 18ms. Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/romstage.c M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/87089/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76 Gerrit-Change-Number: 87089 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: Add allocation of a buffer for pvmfw within cbmem
by Bartłomiej Grzesik (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Jakub "Kuba" Czapiga, Konrad Adamczyk. Hello Jakub "Kuba" Czapiga, Konrad Adamczyk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87107?usp=email to look at the new patch set (#2). Change subject: Add allocation of a buffer for pvmfw within cbmem ...................................................................... Add allocation of a buffer for pvmfw within cbmem This change adds an allocation of an empty buffer for the Android protected virtual machine firmware within cbmem. The buffer will be filled by the payload and the purpose is to just reserve the memory. cbmem is used to make sure that the region won't overlap with other reserved regions or device regions. BUG=b:354045389 BUG=b:359340876 TEST=Check if pvmfw buffer is available for depthcharge BRANCH=firmware-android-15949.B Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7 Signed-off-by: Bartłomiej Grzesik <bgrzesik(a)google.com> --- M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/vendorcode/google/Kconfig M src/vendorcode/google/Makefile.mk A src/vendorcode/google/pvmfw_cbmem.c 6 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/87107/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7 Gerrit-Change-Number: 87107 Gerrit-PatchSet: 2 Gerrit-Owner: Bartłomiej Grzesik <bgrzesik(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com>

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