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[L] Change in coreboot[main]: Documentation: Update cbmem.md with more information
by Martin L Roth (Code Review) 06 Apr '25

06 Apr '25

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87193?usp=email ) Change subject: Documentation: Update cbmem.md with more information ...................................................................... Documentation: Update cbmem.md with more information Change-Id: I2b3eecdf994d4d5b48eacb3ae695efbb5640eb8b Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M Documentation/getting_started/cbmem.md 1 file changed, 344 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/87193/1 diff --git a/Documentation/getting_started/cbmem.md b/Documentation/getting_started/cbmem.md index 13e6cf8..f752a45 100644 --- a/Documentation/getting_started/cbmem.md +++ b/Documentation/getting_started/cbmem.md @@ -1,41 +1,361 @@ # CBMEM high table memory manager ## Introduction + CBMEM (coreboot memory) is a dynamic memory infrastructure used in coreboot to store runtime data structures, logs, and other information -that needs to persist across different boot stages. CBMEM is crucial -for maintaining state and logging information across different stages -of the coreboot boot process. +that needs to persist across different boot stages, and even across warm +boots. CBMEM is crucial for maintaining state and information through +the coreboot boot process. + +Its key responsibilities include: +- Providing a stable storage area for critical boot data +- Managing console logging +- Storing configuration tables for hand off to payloads +- Maintaining timestamps for performance analysis +- Preserving boot state during S3 suspend/resume cycles +- Storing data such as ACPI tables, SMBIOS tables and coreboot tables + which are used at runtime + ## Creation and Placement -CBMEM is initialized by coreboot during romstage, but is used mainly in -ramstage for storing data such as coreboot and ACPI tables, SMBIOS, -timestamps, stage information, vendor-specific data structures, etc. -For 32-bit builds, CBMEM is typically located at the highest usable -DRAM address below the 4GiB boundary. For 64-bit builds, while there -is no strict upper limit, it is advisable to follow the same guidelines -to prevent access or addressing issues. Regardless of the build type, -the CBMEM address must remain consistent between romstage and ramstage. +CBMEM is initialized by coreboot during romstage, but is used mainly in +ramstage for storing any data that needs to be saved for more than a +short period of time. + +For 32-bit builds, CBMEM is typically located at the highest usable DRAM +address below the 4GiB boundary. For 64-bit builds, while there is no +strict upper limit, it is advisable to follow the same guidelines to +prevent access or addressing issues. Regardless of the build type, the +CBMEM address must remain consistent between romstage and ramstage. Each platform may need to implement its own method for determining the `cbmem_top` address, as this can depend on specific hardware configurations and memory layouts. -## Usage + +## Architecture Overview + Each CBMEM region is identified by a unique ID, allowing different -components to store and retrieve their data during runtime. The ID is a -32-bit value that optionally encodes characters to indicate the type or -source of the data. +components to store and retrieve their data during runtime. -Upon creating an entry, a block of memory is allocated of the requested -size from the reserved CBMEM region. This region persists across warm -reboots, making it useful for debugging and passing information to -payloads. +Upon creating an entry, a block of memory of the requested size is +allocated from the reserved CBMEM region. This region typically persists +across warm reboots, making it useful for debugging and passing +information to payloads. -Note that CBMEM is implemented as imd (in-memory database), meaning -it grows downwards in memory from the provided upper limit, and only -the latest added entry may be removed. +CBMEM is implemented as a specialized in-memory database (IMD) system +that grows downward from a defined upper memory limit. This means that +only the latest added entry may be removed. -The `cbmem` tool in `/util` can be used to list and access entries -using their ID. +```text +High Memory ++----------------------+ <- cbmem_top +| Root Pointer | +|----------------------| +| Root Structure | +|----------------------| +| Entry 1 | +|----------------------| +| Entry 2 | +|----------------------| +| ... | +| (grows downward) | ++----------------------+ +``` + + +### Core Components + +The CBMEM system consists of several key components: + +1. **Root Pointer**: Located at the very top of CBMEM memory space, + contains a magic number and offset to the Root Structure + +2. **Root Structure**: Contains metadata about the CBMEM region, + including: + - Entry alignment requirements + - Maximum number of entries + - Current number of entries + - Address of the lowest allocated memory + +3. **Entries**: Individual allocations within CBMEM, identified by: + - 32-bit ID (often encoding ASCII characters for readability) + - Size information + - Magic validation value + +4. **IMD Implementation**: The underlying memory management system + that handles allocation, deallocation, and entry management + + +## Memory Layout and Initialization + +CBMEM is positioned at the top of available system RAM, typically +just below the 4GiB boundary for 32-bit builds. This placement +ensures compatibility with legacy code while allowing CBMEM to +retain its contents across warm resets. + + +### CBMEM Location Determination + +Each platform must implement a `cbmem_top_chipset()` function +that returns the physical address where CBMEM should be located. +This address must be consistent across coreboot stages and is +determined based on: + +- Available physical memory +- Architecture-specific constraints +- BIOS/chipset requirements + + +### Initialization Process + +CBMEM is initialized in a multi-step process: + +1. **Early Initialization**: A small console buffer is created in during + bootblock and romstage + +2. **RAM Initialization**: The full CBMEM area is established in + ramstage + +3. **Normal Operation**: + - In a normal boot, CBMEM is created fresh + - Size and alignment values are specified + - Initial entries are allocated + +4. **Recovery Operation**: + - During S3 resume, CBMEM structure is recovered from memory + - Content is validated using magic numbers and checksums + - All existing entries remain accessible + + +## Entry Management + +CBMEM entries are identified by a 32-bit ID, often encoding ASCII +characters to indicate their purpose (for example, "CNSL" for console). + +### Entry Creation + +```c +void *cbmem_add(u32 id, u64 size); +``` + +This function: +- Searches for an existing entry with the given ID +- If found, returns the existing entry (size is ignored) +- If not found, allocates a new entry of the requested size +- Returns a pointer to the entry's data area + + +### Entry Access + +```c +void *cbmem_find(u32 id); +``` + +This function: +- Searches for an entry with the specified ID +- Returns a pointer to the entry's data area if found +- Returns NULL if the entry does not exist + + +### Entry Removal + +```c +int cbmem_entry_remove(const struct cbmem_entry *entry); +``` + +This function: +- Removes the specified entry if it was the last one added +- Returns 0 on success, negative value on failure +- Note: Due to the downward-growing design, only the most recently + added entry can be removed + + +## CBMEM Console Implementation + +The CBMEM console is a circular buffer used for capturing log messages +across all boot stages. It is one of the most widely used CBMEM +features. The size of this buffer is determined by the +`CONFIG_CBMEM_CONSOLE_SIZE` Kconfig option. + + +### Console Structure + +```c +struct cbmem_console { + u32 size; // Size of the buffer + u32 cursor; // Current write position and flags + u8 body[]; // Actual data buffer +}; +``` + +Key features: +- The high bit of `cursor` indicates overflow condition +- Only the lower 28 bits of `cursor` are used as position +- Supports ring-buffer operation when full + + +### Console Operation + +1. **Initialization**: A console entry is created in CBMEM with ID + `CBMEM_ID_CONSOLE` (0x434f4e53 - 'CONS') + +2. **Writing**: Log messages are written byte-by-byte using + `cbmemc_tx_byte()` which: + - Adds data to the current cursor position + - Advances the cursor + - Sets the overflow flag when wrapping around + +3. **Stage Transition**: When transitioning between boot stages: + - Pre-RAM console contents are copied to the main CBMEM console + - Any overflow condition is preserved and noted + - The process ensures no log messages are lost + + +## Common CBMEM Entry Types + +CBMEM contains various data structures used by different coreboot +components: + +- **Console**: Log messages from all boot stages (`CBMEM_ID_CONSOLE`) +- **Timestamps**: Performance metrics (`CBMEM_ID_TIMESTAMP`) +- **ACPI Tables**: ACPI data for OS handoff (`CBMEM_ID_ACPI`) +- **coreboot Tables**: System information (`CBMEM_ID_CBTABLE`) +- **Memory Information**: RAM configuration (`CBMEM_ID_MEMINFO`) +- **Stage Cache**: Code/data for faster S3 resume +- **ROM/CBFS Cache**: Cached ROM content +- **Vendor-specific**: Platform-dependent structures + +A complete list of IDs is defined in +`src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h`. + + +## Integration with Boot Stages + +CBMEM interacts differently with each coreboot boot stage. + + +### Bootblock/Romstage + +- Uses cache-as-RAM for temporary console storage +- Limited CBMEM functionality before RAM initialization +- Sets up initial timestamp entries + + +### Ramstage + +- Full CBMEM initialization or recovery +- All entries become accessible +- Most coreboot subsystems interact with CBMEM +- Console logging is fully operational + + +### Payload Handoff + +- CBMEM contents are preserved when transferring to the payload +- Entries are made available via coreboot tables +- Common payloads (SeaBIOS, GRUB, etc.) can access CBMEM data + + +## Platform-Specific Considerations + +Different platforms have unique requirements for CBMEM implementation. + + +### x86 Platforms + +- CBMEM typically located just below 4GiB +- Often integrates with ACPI resume and SMM operations +- May need to accommodate memory reserved by legacy components + + +### ARM/RISC-V Platforms + +- More flexibility in CBMEM placement +- Must coordinate with platform-specific memory controllers +- Memory topology can vary significantly between implementations + + +## CBMEM Hooks + +CBMEM provides a hook mechanism to allow subsystems to perform +initialization or recovery operations when CBMEM becomes available: + +```c +CBMEM_CREATION_HOOK(hook_function); // First-time creation only +CBMEM_READY_HOOK(hook_function); // Any CBMEM initialization +CBMEM_READY_HOOK_EARLY(hook_function); // Early CBMEM initialization +``` + +These macros register functions to be called when CBMEM is initialized, +allowing components to set up their CBMEM entries at the appropriate time. + + +## Debugging and Utilities + +### CBMEM Utility + +The `cbmem` utility provides direct access to CBMEM contents on a +running system. It needs to be built from the coreboot source tree using +`make -C util/cbmem`. Common uses include: + +- Listing all CBMEM entries (`cbmem -l`) +- Viewing console logs (`cbmem -c`) +- Analyzing timestamps (`cbmem -t`) +- Extracting specific entries by ID (`cbmem -e <ID>`) + + +### Debugging Techniques + +- CBMEM console contents can be dumped to UART for debugging if serial + output is enabled. +- The console overflow flag (`cbmem -c` output) helps identify if logs + were truncated. +- Size validation within CBMEM helps detect potential memory corruption. +- Magic numbers provide integrity validation for CBMEM structures. +- Enabling `CONFIG_CBMEM_CHECKS` in Kconfig adds extra sanity checks + that can help catch issues during development. + + +## Limitations + +While CBMEM is a powerful tool, it has some inherent limitations: + +- **Downward Growth**: The stack-like allocation (growing downwards) + means that only the most recently added entry can be removed. This + prevents fragmentation but limits flexibility in freeing memory. +- **Fixed Size**: Once CBMEM is initialized in ramstage, its total size + and top address (`cbmem_top`) are fixed. Entries cannot be resized + after allocation. +- **Platform Complexity**: Determining the correct `cbmem_top` can be + complex on some platforms due to varying memory maps and reserved + regions. + + +## Best Practices for Developers + +When working with the CBMEM subsystem: + +1. **Alignment**: Always respect the alignment requirements of the + CBMEM tier (`IMD_ROOT` vs `IMD_SMALL`) you are using. + +2. **ID Selection**: Use unique, meaningful IDs for new entries, + preferably encoding ASCII characters for readability (see + `cbmem_id.h`). + +3. **Size Estimation**: Allocate sufficient space initially, as + entries cannot be resized. + +4. **Memory Conservation**: Be mindful of limited memory resources, + especially on constrained platforms. Avoid storing excessively large + data structures in CBMEM unless necessary. + +5. **Persistence**: Remember that CBMEM contents persist across + warm reboots (like S3 resume) but not across full system resets + (cold boots). + +6. **Entry Ordering**: Consider that only the most recently added + entry can be removed, which might influence your allocation strategy + if you anticipate needing to free space. -- To view, visit https://review.coreboot.org/c/coreboot/+/87193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b3eecdf994d4d5b48eacb3ae695efbb5640eb8b Gerrit-Change-Number: 87193 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add p8b75-v variant
by Keith Hui (Code Review) 06 Apr '25

06 Apr '25

Attention is currently required from: Angel Pons, Felix Held. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85792?usp=email ) Change subject: mb/asus/p8x7x-series: Add p8b75-v variant ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85792/comment/fb2717f5_d4e9c660?us… : PS3, Line 21: to use both to build a 16MiB flash space but that's to be confirmed. > Firmware update size should tell if it's 8 or 16 MiB: it's a capsule with a 8 MiB body. […] Looks like the vendor update is the BIOS/upper 8MiB only and does not include the bottom half with IFD and ME. It isn't dual BIOS - mostly because all B75 boards use the 5MB ME firmware, like Q77 boards. I dug up the P8Q77-M boardview I have, and it also has two flash chips. Q77 also uses 5MB ME. Will update commit message to resolve any doubts. This "capsule" for other boards with only 8MiB flash is the complete image with an extra 2KiB header. File src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout: https://review.coreboot.org/c/coreboot/+/85792/comment/134aec21_2d8a2263?us… : PS3, Line 30: 425 1 e 9 audio_panel_type > Missing default? Will fix with next patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/85792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Gerrit-Change-Number: 85792 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 06 Apr 2025 20:33:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/asus/p8z77-v: Apply vendor PCH interrupt mapping
by Keith Hui (Code Review) 06 Apr '25

06 Apr '25

Attention is currently required from: Bill XIE. Hello Bill XIE, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86191?usp=email to look at the new patch set (#6). Change subject: mb/asus/p8z77-v: Apply vendor PCH interrupt mapping ...................................................................... mb/asus/p8z77-v: Apply vendor PCH interrupt mapping Got this information from Bill Xie while troubleshooting CB:85413. Apply the differences from vendor to coreboot. Change-Id: I56f4314eca101cdfcac12594115d373472d1e1db Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/86191/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56f4314eca101cdfcac12594115d373472d1e1db Gerrit-Change-Number: 86191 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEP
by Matt DeVillier (Code Review) 06 Apr '25

06 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87153?usp=email ) Change subject: mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f Gerrit-Change-Number: 87153 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 06 Apr 2025 19:00:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Enable DDC for DDIA
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86914?usp=email ) Change subject: mb/starlabs/*: Enable DDC for DDIA ...................................................................... mb/starlabs/*: Enable DDC for DDIA Enable DDC so that GOP can read the backlight brightness from EDID. This avoids FSP repeatedly trying and failing to read it, and also stops the backlight brightness not being restored correctly in Linux. Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86914 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 99e89ae..a859368 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -20,7 +20,7 @@ device domain 0 on device ref igpu on register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 7588e93..c11cc71 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -32,7 +32,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index 73708f5..f0f16c4 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -52,7 +52,7 @@ register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 1905e3e..645bd50 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -34,7 +34,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index e75df6f..a73c4f6 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -33,7 +33,7 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index eb711a0..d9996ca 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -62,7 +62,7 @@ register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end -- To view, visit https://review.coreboot.org/c/coreboot/+/86914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe Gerrit-Change-Number: 86914 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Enable DDC for DDIA
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86914?usp=email ) Change subject: mb/starlabs/*: Enable DDC for DDIA ...................................................................... Patch Set 1: (1 comment) File src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb: https://review.coreboot.org/c/coreboot/+/86914/comment/071a607f_d78b02b5?us… : PS1, Line 23: DDI_ENABLE_DDC > Sanity check please Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe Gerrit-Change-Number: 86914 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Apr 2025 18:57:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Tidy GPIO comments for SATA
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87173?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/tgl: Tidy GPIO comments for SATA ...................................................................... mb/starlabs/starbook/tgl: Tidy GPIO comments for SATA This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 6cf5fab..b6f1526 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -44,6 +44,9 @@ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* Reset */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* Enable */ + /* SATA */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* PEDET */ + /* Wireless */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* BRI Data */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* BRI Response */ @@ -104,8 +107,6 @@ PAD_NC(GPP_A7, NONE), /* A10: WLAN_PCM_IN */ PAD_NC(GPP_A10, NONE), - /* A12: SATAGP_1 */ - PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* A13: Not Connected */ PAD_NC(GPP_A13, NONE), /* A14: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21 Gerrit-Change-Number: 87173 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Correct wireless GPIO group
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87171?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/tgl: Correct wireless GPIO group ...................................................................... mb/starlabs/starbook/tgl: Correct wireless GPIO group Change-Id: I6565c3fa3d171625b0d3e538371d53d6449db180 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87171 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 3c5158d..6cf5fab 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -49,7 +49,8 @@ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* BRI Response */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* RGI Data */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* RGI Response */ - PAD_NC(GPP_F6, NONE), /* Modem Clock Request */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), /* RF Reset */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* Modem Clock Request */ /* Display */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* eDP Hot Plug */ @@ -101,10 +102,6 @@ /* A7: WLAN_PCM_CLK */ PAD_NC(GPP_A7, NONE), - /* A8: WLAN_PCM_RST */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), - /* A9: WLAN_PCM_CLKREQ0 */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* A10: WLAN_PCM_IN */ PAD_NC(GPP_A10, NONE), /* A12: SATAGP_1 */ @@ -280,6 +277,8 @@ PAD_NC(GPP_F4, NONE), /* F5: GPPC_F5_MODEM_CLKREQ */ PAD_NC(GPP_F5, NONE), + /* F6: */ + PAD_NC(GPP_F6, NONE), /* F7: BIOS_REC */ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* F8: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6565c3fa3d171625b0d3e538371d53d6449db180 Gerrit-Change-Number: 87171 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Add comments for eSPI GPIO
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87170?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/tgl: Add comments for eSPI GPIO ...................................................................... mb/starlabs/starbook/tgl: Add comments for eSPI GPIO This is a non-functional change, and just makes it easier to read. Change-Id: I89028c87eeab95bf4e7a35471072bb41d02b4e6c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index ddf7db7..3c5158d 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -25,6 +25,15 @@ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* Sleep S4 */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* Bluetooth Suspend */ + /* eSPI */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A0, UP_20K, DEEP, NF1), /* eSPI IO 0 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A1, UP_20K, DEEP, NF1), /* eSPI IO 1 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A2, UP_20K, DEEP, NF1), /* eSPI IO 2 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A3, UP_20K, DEEP, NF1), /* eSPI IO 3 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A4, UP_20K, DEEP, NF1), /* eSPI CS 0 */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A5, UP_20K, DEEP, NF1), /* eSPI Clk */ + // PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A6, NONE, DEEP, NF1), /* eSPI Reset */ + /* Touchpad */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* Data */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* Clock */ @@ -90,7 +99,6 @@ /* GPD11: PM_LANPHY_EN */ PAD_NC(GPD11, NONE), - /* A6: Not Connected(TP764) */ /* A7: WLAN_PCM_CLK */ PAD_NC(GPP_A7, NONE), /* A8: WLAN_PCM_RST */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89028c87eeab95bf4e7a35471072bb41d02b4e6c Gerrit-Change-Number: 87170 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Disconnect unused GPIOs
by Sean Rhodes (Code Review) 06 Apr '25

06 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87169?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/tgl: Disconnect unused GPIOs ...................................................................... mb/starlabs/starbook/tgl: Disconnect unused GPIOs These pins are not used, so configure them accordingly. Change-Id: If82741382c113b2f05078e0d24690943c9053421 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87169 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 14 insertions(+), 14 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 07b455f..ddf7db7 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -80,15 +80,15 @@ /* GPD2: LAN_WAKE# */ PAD_NC(GPD2, NONE), /* GPD6: SIO_SLP_A# */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_NC(GPD6, NONE), /* GPD7: PCH_TBT_PERST# */ PAD_CFG_GPO(GPD7, 0, PLTRST), /* GPD9: SIO_SLP_WLAN# */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + PAD_NC(GPD9, NONE), /* GPD10: SIO_SLP_S5# */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + PAD_NC(GPD10, NONE), /* GPD11: PM_LANPHY_EN */ - PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + PAD_NC(GPD11, NONE), /* A6: Not Connected(TP764) */ /* A7: WLAN_PCM_CLK */ @@ -108,7 +108,7 @@ /* A15 Not Connected */ PAD_NC(GPP_A15, NONE), /* A16: USB2_OCB_3 */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A16, NONE), /* A17: Not Connected */ PAD_NC(GPP_A17, NONE), /* A19 Not Connected */ @@ -133,11 +133,11 @@ /* B8: Not Connected */ PAD_NC(GPP_B8, NONE), /* B9: PWR_MON_I2C_SDA_R */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B9, NONE), /* B10: PWR_MON_I2C_SCL_R */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), /* B12: PM_SLP_S0_N */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_NC(GPP_B12, NONE), /* B14: FPS_RST_N */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), /* B15: Not Connected */ @@ -162,9 +162,9 @@ /* C2: SMBALERT_N */ PAD_CFG_GPO(GPP_C2, 0, DEEP), /* C3: SML0_CLK */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_NC(GPP_C3, NONE), /* C4: SML0_DATA */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C4, NONE), /* C5: SML0ALERT_IN */ PAD_CFG_GPO(GPP_C5, 0, DEEP), /* C9: Not Connected */ @@ -180,9 +180,9 @@ /* C15: TPM_RST */ PAD_NC(GPP_C15, NONE), /* C18: TOUCH_I2C_SDA */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_NC(GPP_C18, NONE), /* C19: TOUCH_I2C_CLK */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C19, NONE), /* C22: Not Connected */ PAD_NC(GPP_C22, NONE), /* C23: WLAN_WAKE_N */ @@ -232,7 +232,7 @@ /* E2: Not Connected */ PAD_NC(GPP_E2, NONE), /* E3: FPS_INT */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + PAD_NC(GPP_E3, NONE), /* E4: Not Connected */ PAD_NC(GPP_E4, NONE), /* E5: Not Connected */ @@ -244,7 +244,7 @@ /* E8: EC_SLP_S0IX_N */ PAD_NC(GPP_E8, NONE), /* E9: USB2_TCP01_OC_N */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_NC(GPP_E9, NONE), /* E10: SPI1_TCH_PNL_CS_N */ PAD_NC(GPP_E10, NONE), /* E11: SPI1_CLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If82741382c113b2f05078e0d24690943c9053421 Gerrit-Change-Number: 87169 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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