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Change subject: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE
......................................................................
mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE
This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported.
The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards.
This option was previously enabled at the SoC level for Pantherlake,
but is now being enabled specifically for these mainboards.
BUG=b:400550435
TEST=Build the Fatcat and Felino targets. Verify that the eSOL works
fine.
Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/fatcat/Kconfig
M src/soc/intel/pantherlake/Kconfig
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/87236/2
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Change subject: doc/arch/x86: Add MP-Init documentation
......................................................................
Patch Set 5:
(6 comments)
File Documentation/arch/x86/mp_init.md:
PS5:
Please reflow lines to about 72 characters: https://doc.coreboot.org/getting_started/writing_documentation.html#basic-a…https://review.coreboot.org/c/coreboot/+/86772/comment/58a07d16_6eaadc4c?us… :
PS5, Line 31: init_bsp()
Enclose function name in backticks so that it renders as an inline code block
```suggestion
First `init_bsp()` initializes the bootstrap processor. After this we are ready to initialize all other logical processors (the APs). On a hyperthreading CPU that means all physical threads. We need initialize all APs from scratch. Among other we need setup a stack, GDT, IDT, caching and a fewer other things. Since we need to setup a stack, we need to start in assembly for all APs. That is what the `src/cpu/x86/sipi_vector.S` is for.
```
https://review.coreboot.org/c/coreboot/+/86772/comment/ac977440_38fc02eb?us… :
PS5, Line 36: ap_init()
Same here
```suggestion
The assembly code will do the bare minimum initialization before eventually jumping to c-code. That c-code is usually the `ap_init()` function. But first we need to tell the APs to wake up and start executing the SIPI vector code. We can use the "Interrupt Command Register" to issue interrupts to other local APICs (and therefore other logical processors) causing them to wake up and execute from an address of our choice (with certain restrictions).
```
https://review.coreboot.org/c/coreboot/+/86772/comment/6e0e524a_740fd0e7?us… :
PS5, Line 56: setting
Capitalize
```suggestion
### Setting up SMM
```
https://review.coreboot.org/c/coreboot/+/86772/comment/1e3ebf55_1af599ff?us… :
PS5, Line 58: implemented in SMM.
: Now
Markdown requires a blank line in between paragraphs, otherwise it renders as the same paragraph.
https://review.coreboot.org/c/coreboot/+/86772/comment/a5c8afa6_97f2a2b2?us… :
PS5, Line 59: jumps.
: Unf
Same here, add a blank line
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Change subject: soc/mediatek/mt8196: Add validity check for PI_IMG
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/mt8196/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/86352/comment/7ae274bf_23034ba5?us… :
PS5, Line 122: $(PI_IMG_OUT)
> The CONFIG_PI_IMG_FIRMWARE will be added twice. […]
That's my mistake.
However, now I realized that this approach is problematic, as `$(wildcard ...)` won't find anything in line 128 below. Decided to switch to a different approach.
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Change subject: soc/mediatek/mt8196: Add validity check for PI_IMG
......................................................................
soc/mediatek/mt8196: Add validity check for PI_IMG
Call check-pi-img.py to perform validity check for the PI_IMG firmware
file.
BUG=none
TEST=emerge-rauru coreboot
TEST=cbfstool coreboot.rom print | grep pi_img
BRANCH=rauru
Change-Id: I7b8085c1229c1a7a8cad904e166471ff8bda5cfb
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8196/Makefile.mk
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86352/7
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Change subject: Documentation,util: Run util_readme.sh to regen *.md
......................................................................
Patch Set 1:
(1 comment)
File Documentation/util.md:
https://review.coreboot.org/c/coreboot/+/87224/comment/dd1c4263_cbfe5b61?us… :
PS1, Line 73: c
> Why does `convert` become lower case ?
util_readme.sh just copies whatever is in the `description.md` file for a utility. Looks like these series of commits occured:
- Commit 81e0d689c078 ("Documentation: Move intelp2m from description.md to Documention") added the lowercase "convert the configuration DW0/1..." text to `util/intelp2m/description.md`
- Commit 56846091f136 ("util, Documentation: Run util_readme.sh to regen util.md") updated Documentation/util.md to match using the script.
- Commit da54bd60af60 ("Documentation: Update information about intelp2m") manually updated `Documentation/util.md` (without using the script) to the "Convert the inteltool ..." that's currently there, so in effect this patch effectively reverts da54bd60af60 and restores the text from 56846091f136.
So I guess `util/intelp2m/description.md` should have been updated to the "Convert the inteltool register dump..." text before regenerating the *.md files using `util_readme.sh` so as to not lose the updated description from da54bd60af60
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Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/3bfa8ee4_6bfd4c8e?us… :
PS7, Line 104: 0x40
Let Setup = /sys/firmware/efi/efivars/Setup-ec87d643-eba4-4bb5-a1e5-3f3e36b20da9 , my result is:
PCIEX1_2: Setup[0x820] == 0, Setup[0x824] == 2;
ASM1061: Setup[0x820] == 0, Setup[0x824] == 0;
x4: Setup[0x820] == 0, Setup[0x824] == 1;
Besides, on patchset 7, when (force_asm1061 == false), if a card is present on PCIEX1_2 X_QSW_SEL2,3,4 is 111, and if not present, X_QSW_SEL2,3,4 is correctly 110.
If a descriptor with (PCIEPCS1 == 1) is flashed with patchset 7, PCIEX16_3 can be confirmed working with x2, with on-board ASM1061 working with X_QSW_SEL2,3,4 being 010. PCIEX1_2 remains not working in this mode, with X_QSW_SEL2,3,4 being 011 and the following log:
> [DEBUG] PCI: 00:00:1c.3 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 06
[INFO ] POST: 0x24
[INFO ] POST: 0x25
[INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
[WARN ] PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed.
[DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs
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