coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST
by Sean Rhodes (Code Review) 09 Apr '25

09 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87213?usp=email ) Change subject: mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST ...................................................................... mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRST Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP, renders the SSD inaccessible on S3 exit as it conflicts with the RTD3 driver. Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87213 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/tgl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index b6f1526..2794ea4 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -42,7 +42,7 @@ /* SSD */ PAD_NC(GPP_D8, NONE), /* Clock Request 3 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* Reset */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), /* Enable */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* Enable */ /* SATA */ PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* PEDET */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Gerrit-Change-Number: 87213 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/guren: Add touch screen FTSC1000 support
by Brian Hsu (Code Review) 09 Apr '25

09 Apr '25

Brian Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87238?usp=email ) Change subject: mb/google/nissa/var/guren: Add touch screen FTSC1000 support ...................................................................... mb/google/nissa/var/guren: Add touch screen FTSC1000 support New Touchscreen function for Guren project. 1. Extend 1 bit [34] for the TOUCHSCREEN_SOURCE. SSFC range for TOUCHSCREEN_SOURCE is bit[32:34]. 2. Touchscreen panel: HKO RB116AS01-2, and set TOUCHSCREEN_FTSC1000 to value "3" BUG=b:391281767 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/overridetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/87238/1 diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb index 0e10689..3306e8a 100644 --- a/src/mainboard/google/brya/variants/guren/overridetree.cb +++ b/src/mainboard/google/brya/variants/guren/overridetree.cb @@ -29,6 +29,7 @@ option TOUCHSCREEN_UNPROVISIONED 0 option TOUCHSCREEN_ELAN0001 1 option TOUCHSCREEN_ILIT2901 2 + option TOUCHSCREEN_FTSC1000 3 end end @@ -369,6 +370,25 @@ probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ILIT2901 end end + + chip drivers/i2c/hid + register "generic.hid" = ""FTSC1000"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "30" + register "generic.stop_off_delay_ms" = "10" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_FTSC1000 + end + end end #I2C1 device ref i2c2 on chip drivers/i2c/sx9324 -- To view, visit https://review.coreboot.org/c/coreboot/+/87238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9 Gerrit-Change-Number: 87238 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes
by Keith Hui (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ...................................................................... Patch Set 8: (2 comments) Patchset: PS8: Now is when you need that extra SPI flash chip and working coreboot copy and a couple leap of faith - I just posted a complete implementation. Setting pciex16_3_bandwidth between 0 and 1 should not trigger a IFD reflash and you can play with them. Let me know how it works, now that the key logic is now in ramstage. File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/dbf021c9_f82a2d80?us… : PS7, Line 104: 0x40 > Let Setup = /sys/firmware/efi/efivars/Setup-ec87d643-eba4-4bb5-a1e5-3f3e36b20da9 , my result is: […] So efivarfs does prepend the 4-byte attributes to EFI variables. Looks like whatever logic around PCIEX1_2_NOT_PRESENT failed to set the GPIO lines at all when a card is present, and put the GPIOs in that invalid state. Great to hear that x2 actually works. And according to owners manual, the values 0-2 represents Auto, x4, x1 respectively, which is the question I was trying to answer. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 8 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 06:53:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE
by Jayvik Desai (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87236?usp=email ) Change subject: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103 Gerrit-Change-Number: 87236 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 06:48:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes
by Keith Hui (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Hello Bill XIE, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85413?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ...................................................................... mb/asus/p8z77-v: Add support to reconfigure PCIe lanes Bill Xie documented in his initial code drop that he was unsuccessful in reproducing all the PCIe configurations possible with vendor firmware. I obtained a boardview to this board and have identified the PCIe lane topology and the required control signals. There are PCIe slot presence signals wired to GPIOs 34,20,7 for PCIEX1_1,PCIEX1_2,PCIEX16_3 respectively, the last one only sense the presence of a PCIe x4 or larger card. PCIe lanes 1-4 are routed by way of three ASM1440 2-way switches controlled by GP54-GP56 on NCT6779D super I/O chip. PCIe lanes 5-8 are fixed. With these details, it is now possible to attempt to reproduce all the vendor PCIe configurations. 1. Change GPIO20 of PCH to GPIO input so coreboot can detect a card inserted into PCIEX1_2. 2a. Add an nvram option to force PCIe lane 4 to serve ASM1061 and its two SATA 6Gbps ports. 2b. Add an nvram option to allow selecting PCIEX16_3 bandwidth between auto (tries to sense for a card in PCIEX1_2 and prioritize it, subject to #2a, otherwise same as x1), x1, x2 (experimental; disables PCIEX1_1, not a vendor option), x4. 3. Based on (1) and (2), program SIO GPIO5 and soft strap as appropriate. Remove all GPIO5 settings from devicetree so this code has full control. Supporting code around reflashing the PCH soft straps are factored out as a separate unit at asus/p8x7x-series, available via a new Kconfig. This is because p8z77-v_le_plus and Sabertooth Z77 also have similar needs. BUG=https://ticket.coreboot.org/issues/583 Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Makefile.mk M src/mainboard/asus/p8x7x-series/mainboard.c A src/mainboard/asus/p8x7x-series/pcielane.c A src/mainboard/asus/p8x7x-series/pcielane.h M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default M src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb A src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c 11 files changed, 385 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85413/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 8 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping
by Subrata Banik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Mac Chiang, Pranava Y N. Subrata Banik has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) Change subject: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 06:35:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE
by Pranava Y N (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Subrata Banik. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87236?usp=email ) Change subject: mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFE ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103 Gerrit-Change-Number: 87236 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 06:27:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping
by Mac Chiang (Code Review) 09 Apr '25

09 Apr '25

Mac Chiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) Change subject: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping ...................................................................... mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping The DMIC_CLK_A1 and DMIC_DAT_A1 function pins on GPP_D16 and GPP_D17 are configured to NF3. BUG=b:378629979 Test=emerge-fatcat coreboot Verify DMIC recording functionality. Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 --- M src/mainboard/google/fatcat/variants/felino/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/87237/1 diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 3b2a693..a70e9fe 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -182,9 +182,9 @@ /* GPP_D15: NC */ PAD_NC(GPP_D15, NONE), /* GPP_D16: PCH_DMIC_CLK1 */ - PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), /* GPP_D17: PCH_DMIC_DATA1 */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), /* GPP_D18: PCIE_CLKREQ_SD_N */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19: NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brya/var/guren: Add Stylus Pen Function
by Daniel Peng (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Daniel Peng has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/87235?usp=email ) Change subject: mb/google/brya/var/guren: Add Stylus Pen Function ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Hi Googler, Ready to review if no concern. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/87235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46d679d29b35d0f4fc70d63b74975d3bdfc40b7b Gerrit-Change-Number: 87235 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 05:52:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/mtkheader: Rename to util/mediatek
by Yu-Ping Wu (Code Review) 09 Apr '25

09 Apr '25

Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/87225?usp=email ) Change subject: util/mtkheader: Rename to util/mediatek ...................................................................... Patch Set 1: (1 comment) File util/README.md: https://review.coreboot.org/c/coreboot/+/87225/comment/992f4b90_5a0b7f09?us… : PS1, Line 83: `Python3` > should move to the end of the above line ? It's formatted by the tool, possibly because of the line length limit -- To view, visit https://review.coreboot.org/c/coreboot/+/87225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca Gerrit-Change-Number: 87225 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 05:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit April 2025