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Change subject: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/lpc.h:
https://review.coreboot.org/c/coreboot/+/86583/comment/91ec18fb_af296f3b?us… :
PS1, Line 106: ROM_ADDRESS_RANGE3_START
> Move this up, after ROM_ADDRESS_RANGE2_END.
Shouldn't it be moved down after LPC_WIDEIO2_GENERIC_PORT to keep numerical order?
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Change subject: soc/intel/pantherlake: Add early shutdown notification hook
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86476/comment/3d682372_77494691?us… :
PS4, Line 16: This patch also refactor `fill_fspm_sign_of_life` to use UX API
: `ux_inform_user_of_update_operation` for memory training notification.
:
> > Can we move this to another CL? […]
Acknowledged
CB:86592
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Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Ronak Kanabar.
Hello Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Ronak Kanabar, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
......................................................................
drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
This commit introduces an early low-battery shutdown mechanism during
FSP memory initialization. This is particularly important during
firmware updates, where memory training can consume significant power
and lead to abrupt shutdowns, potentially corrupting the firmware.
The changes include:
- Adding platform_display_early_shutdown_notification() to notify the
user of the impending shutdown.
- Checking platform_is_low_battery_shutdown_needed() to determine if a
shutdown is necessary.
- Implementing a shutdown sequence if low battery is detected during
memory init, especially when no MRC cache is found (i.e. firmware
update).
- Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT
so that FSP-M (uGOP) can display a message.
This prevents firmware update corruption due to low battery.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
2 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86452/8
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Change subject: soc/intel/pantherlake: Add early shutdown notification hook
......................................................................
soc/intel/pantherlake: Add early shutdown notification hook
This commit display UX message for low-battery shutdown using
platform_display_early_shutdown_notification().
This commit also enables the HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR
Kconfig option, which is required for displaying the VGA text message
during early shutdown.
BUG=b:339673254
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Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/86476/5
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Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
Hi Paul, the information was updated, please help to check is there any remaining question. Thanks a lot.
Commit Message:
https://review.coreboot.org/c/coreboot/+/86535/comment/707b20cc_b8186e6b?us… :
PS1, Line 7: supported
> *7 supported* or just *7*
Done
https://review.coreboot.org/c/coreboot/+/86535/comment/7aee2cf8_fab9e6de?us… :
PS1, Line 13: K3KL8L80CM-MGCT 0 (0000)
: K3KL6L60GM-MGCT 1 (0001)
: H58G56AK6BX069 2 (0010)
: H9JCNNNBK3MLYR-N6E 3 (0011)
: H58G66AK6BX070 4 (0100)
: K3KL9L90CM-MGCT 5 (0101)
: K3LKBKB0BM-MGCP 2 (0010)
> Please mention the vendors.
Done
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Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
......................................................................
mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name Vendor Model Spec ID to assign
K3KL8L80CM-MGCT Samsung LPDDR5X 7500 32Gb 0 (0000)
K3KL6L60GM-MGCT Samsung LPDDR5X 7500 16Gb 1 (0001)
H58G56AK6BX069 SK hynix LPDDR5 6400 32Gb 2 (0010)
H9JCNNNBK3MLYR-N6E SK hynix LPDDR5 6400 16Gb 3 (0011)
H58G66AK6BX070 SK hynix LPDDR5 6400 64Gb 4 (0100)
K3KL9L90CM-MGCT Samsung LPDDR5X 7500 64Gb 5 (0101)
K3LKBKB0BM-MGCP Samsung LPDDR5 6400 16Gb 2 (0010)
BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/guren/memory/ \
src/mainboard/google/brya/variants/guren/memory/\
mem_parts_used.txt"
Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232
Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/guren/memory/Makefile.mk
M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt
3 files changed, 28 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86535/2
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