coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Frank Wu, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Frank Wu. ( https://review.coreboot.org/c/coreboot/+/86593?usp=email ) Change subject: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Gerrit-Change-Number: 86593 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 08:51:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions
by Patrick Rudolph (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86583?usp=email ) Change subject: soc/amd/common/block/lpc: Add ROM2 and ROM3 helper functions ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/lpc.h: https://review.coreboot.org/c/coreboot/+/86583/comment/91ec18fb_af296f3b?us… : PS1, Line 106: ROM_ADDRESS_RANGE3_START > Move this up, after ROM_ADDRESS_RANGE2_END. Shouldn't it be moved down after LPC_WIDEIO2_GENERIC_PORT to keep numerical order? -- To view, visit https://review.coreboot.org/c/coreboot/+/86583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a Gerrit-Change-Number: 86583 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 08:43:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence
by Frank Wu (Code Review) 25 Feb '25

25 Feb '25

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86593?usp=email ) Change subject: mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence ...................................................................... mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence Move SSD enable/reset pins to romstage to have more time for initialization. BUG=b:398070426 BRANCH=None TEST=Build francka and do EC reset to check the SSD boots to OS successfully Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/francka/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/86593/1 diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index 6265b16..f2868fc 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -416,6 +416,8 @@ /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { + /* GPP_B16: SOC_SSD2_EN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), /* GPP_C00: SOC_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C01: SOC_SMBDATA */ @@ -424,6 +426,8 @@ PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPP_H17: FP_RST_1V8_OD# */ PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_E03: SOC_SSD2_RST# */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/86593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640 Gerrit-Change-Number: 86593 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86452?usp=email ) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... Patch Set 8: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/86452/comment/54cb2adc_fb7fab6c?us… : PS7, Line 349: /* User has been notified of low battery; safe to power off. */ > Move it to just before power-off call at line#352. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 08:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add early shutdown notification hook
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86476?usp=email ) Change subject: soc/intel/pantherlake: Add early shutdown notification hook ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86476/comment/3d682372_77494691?us… : PS4, Line 16: This patch also refactor `fill_fspm_sign_of_life` to use UX API : `ux_inform_user_of_update_operation` for memory training notification. : > > Can we move this to another CL? […] Acknowledged CB:86592 -- To view, visit https://review.coreboot.org/c/coreboot/+/86476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Gerrit-Change-Number: 86476 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 08:23:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86592?usp=email ) Change subject: soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs ...................................................................... soc/intel/pantherlake: Centralize FSP-M eSOL UX with common APIs Refactor the FSP-M early Sign-of-Life (eSOL) implementation to utilize the UX APIs defined in `ux.c`. This eliminates redundant code and ensures consistent messaging during critical boot phases, such as memory training. BUG=b:339673254 TEST=Verified eSOL message over eDP while booting google/fatcat. Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/86592/1 diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 8de99d2..a8f86a8 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootmode.h> #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> #include <elog.h> @@ -13,7 +12,8 @@ #include <soc/pcie.h> #include <soc/romstage.h> #include <static.h> -#include <ux_locales.h> + +#include "ux.h" #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 @@ -360,31 +360,16 @@ static void fill_fspm_sign_of_life(FSPM_UPD *mupd) { - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - void *vbt; - size_t vbt_size; if (arch_upd->NvsBufferPtr) return; /* To enhance the user experience, let's display on-screen guidance during memory training, acknowledging that the process may require patience. */ - - vbt = cbfs_map("vbt.bin", &vbt_size); - if (!vbt) { - printk(BIOS_ERR, "Could not load vbt.bin\n"); - return; - } - printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); - - m_cfg->VgaInitControl = 1; - m_cfg->VbtPtr = (efi_uintn_t)vbt; - m_cfg->VbtSize = vbt_size; - m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); + ux_inform_user_of_update_operation("memory training", mupd); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/86592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf22c39c21e2357b2a548398700a1488f4ef463a Gerrit-Change-Number: 86592 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Ronak Kanabar. Hello Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86452?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... drivers/intel/fsp2_0: Add early low-battery shutdown during memory init This commit introduces an early low-battery shutdown mechanism during FSP memory initialization. This is particularly important during firmware updates, where memory training can consume significant power and lead to abrupt shutdowns, potentially corrupting the firmware. The changes include: - Adding platform_display_early_shutdown_notification() to notify the user of the impending shutdown. - Checking platform_is_low_battery_shutdown_needed() to determine if a shutdown is necessary. - Implementing a shutdown sequence if low battery is detected during memory init, especially when no MRC cache is found (i.e. firmware update). - Deferring shutdown on systems without MAINBOARD_HAS_EARLY_LIBGFXINIT so that FSP-M (uGOP) can display a message. This prevents firmware update corruption due to low battery. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/86452/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add early shutdown notification hook
by Subrata Banik (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N. Hello Christian Walter, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86476?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add early shutdown notification hook ...................................................................... soc/intel/pantherlake: Add early shutdown notification hook This commit display UX message for low-battery shutdown using platform_display_early_shutdown_notification(). This commit also enables the HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR Kconfig option, which is required for displaying the VGA text message during early shutdown. BUG=b:339673254 TEST=Verified low battery boot event logging and controlled shutdown. Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/86476/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86476?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45c0fb07b984fcde6209631612cb8b4a08ac2041 Gerrit-Change-Number: 86476 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
by Brian Hsu (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel. Brian Hsu has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email ) Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts ...................................................................... Patch Set 2: (3 comments) Patchset: PS2: Hi Paul, the information was updated, please help to check is there any remaining question. Thanks a lot. Commit Message: https://review.coreboot.org/c/coreboot/+/86535/comment/707b20cc_b8186e6b?us… : PS1, Line 7: supported > *7 supported* or just *7* Done https://review.coreboot.org/c/coreboot/+/86535/comment/7aee2cf8_fab9e6de?us… : PS1, Line 13: K3KL8L80CM-MGCT 0 (0000) : K3KL6L60GM-MGCT 1 (0001) : H58G56AK6BX069 2 (0010) : H9JCNNNBK3MLYR-N6E 3 (0011) : H58G66AK6BX070 4 (0100) : K3KL9L90CM-MGCT 5 (0101) : K3LKBKB0BM-MGCP 2 (0010) > Please mention the vendors. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 08:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts
by Brian Hsu (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Brian Hsu, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86535?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts ...................................................................... mb/google/nissa/var/guren: Generate SPD ID for 7 supported memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name Vendor Model Spec ID to assign K3KL8L80CM-MGCT Samsung LPDDR5X 7500 32Gb 0 (0000) K3KL6L60GM-MGCT Samsung LPDDR5X 7500 16Gb 1 (0001) H58G56AK6BX069 SK hynix LPDDR5 6400 32Gb 2 (0010) H9JCNNNBK3MLYR-N6E SK hynix LPDDR5 6400 16Gb 3 (0011) H58G66AK6BX070 SK hynix LPDDR5 6400 64Gb 4 (0100) K3KL9L90CM-MGCT Samsung LPDDR5X 7500 64Gb 5 (0101) K3LKBKB0BM-MGCP Samsung LPDDR5 6400 16Gb 2 (0010) BUG=b:397149037 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/memory/Makefile.mk M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt 3 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86535/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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