coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in coreboot[main]: drivers/usb/intel-bluetooth: Remove the _PR3 Object
by Sean Rhodes (Code Review) 25 Feb '25

25 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86595?usp=email ) Change subject: drivers/usb/intel-bluetooth: Remove the _PR3 Object ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65f206899affd46d791c2ba39235a1af320395d2 Gerrit-Change-Number: 86595 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 11:04:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: driver/usb/intel_bluetooth: Add PS0 and PS3 methods
by Sean Rhodes (Code Review) 25 Feb '25

25 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86507?usp=email ) Change subject: driver/usb/intel_bluetooth: Add PS0 and PS3 methods ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32 Gerrit-Change-Number: 86507 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 25 Feb 2025 11:04:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: treewide: Rename PM4LE -> PML4E
by Angel Pons (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, Maximilian Brune, Patrick Rudolph. Angel Pons has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86587?usp=email ) Change subject: treewide: Rename PM4LE -> PML4E ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730235beea69b3720f080bbade083c2eeed26587 Gerrit-Change-Number: 86587 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 10:57:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85806?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... cpu/x86/64bit: Install extended page tables in BSS On Intel 14nm Xeon-SP every processor supports 1TiB of DRAM. Since MMIO is mapped above usable DRAM, the default page tables in RODATA are not sufficient to cover the high MMIO space. This prevents the use of coreboot's ramstage drivers as they cannot access the PCI BARs residing in high MMIO. Introduce a simple page table generator that installs extended page tables in BSS to access up to 48bit of the virtual address space. TEST: QEMU (that does not support 1GB PT) is able to access up to 512 GiB of memory after installing PT in BSS. IBM/SBP1 (that does support 1GB PT) is able to boot to OS with new page tables installed. Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/qemu-x86/Kconfig M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/mmu.c M src/cpu/x86/Kconfig M src/soc/intel/xeon_sp/Kconfig 5 files changed, 214 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85806/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

1 0

[S] Change in coreboot[main]: soc/amd/glinda: Move AMDFWBODY to upper 16MiB
by Ana Carolina Cabral (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Patrick Rudolph. Ana Carolina Cabral has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86585?usp=email ) Change subject: soc/amd/glinda: Move AMDFWBODY to upper 16MiB ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/birman_plus/Kconfig: https://review.coreboot.org/c/coreboot/+/86585/comment/ae9b5d69_869531d8?us… : PS1, Line 5: BOARD_ROMSIZE_KB_65536 > Isn't it 512-Mbit flash SPI ROM? (from schematics and user guide) Ops, MiB confused me.. sorry -- To view, visit https://review.coreboot.org/c/coreboot/+/86585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifdc8618a87588469eb8801cb73eb25cdca486adf Gerrit-Change-Number: 86585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 10:38:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

1 0

[S] Change in coreboot[main]: soc/amd/glinda: Move AMDFWBODY to upper 16MiB
by Ana Carolina Cabral (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Patrick Rudolph. Ana Carolina Cabral has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86585?usp=email ) Change subject: soc/amd/glinda: Move AMDFWBODY to upper 16MiB ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/birman_plus/Kconfig: https://review.coreboot.org/c/coreboot/+/86585/comment/081e5f85_32841e83?us… : PS1, Line 5: BOARD_ROMSIZE_KB_65536 Isn't it 512-Mbit flash SPI ROM? (from schematics and user guide) -- To view, visit https://review.coreboot.org/c/coreboot/+/86585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifdc8618a87588469eb8801cb73eb25cdca486adf Gerrit-Change-Number: 86585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Feb 2025 10:32:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: cpu/x86/64bit: Allow to map more of the address space
by Patrick Rudolph (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Patrick Rudolph. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86580?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/x86/64bit: Allow to map more of the address space ...................................................................... cpu/x86/64bit: Allow to map more of the address space On AMD platforms the SPI flash can be accessed using the ROM3 mapping in upper MMIO space. To reach the MMIO window the default page tables must be extended to cover the address by default. Add support for a SoC specific default address space being used on x86_64, where the default of 4GiB/512GiB remains. The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option. Used in the following patch to use ROM3 mapping on AMD platforms. TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64 TEST: x86_64 still works on qemu/q35. Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/pt.S M src/cpu/x86/64bit/pt1G.S M src/cpu/x86/Kconfig 3 files changed, 31 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/86580/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462 Gerrit-Change-Number: 86580 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[L] Change in coreboot[main]: mb/qemu-i440fx: refactor qemu flash logic as a separate driver
by Carlos López (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Maximilian Brune, Nicholas Chin, Philipp Hug, ron minnich. Carlos López has posted comments on this change by Carlos López. ( https://review.coreboot.org/c/coreboot/+/85674?usp=email ) Change subject: mb/qemu-i440fx: refactor qemu flash logic as a separate driver ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi Nicholas, would you mind reviewing this? It is fairly similar in intention to: https://review.coreboot.org/c/coreboot/+/85673 -- To view, visit https://review.coreboot.org/c/coreboot/+/85674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee50b29d079564707e414bb92e949c306fb6ad3 Gerrit-Change-Number: 85674 Gerrit-PatchSet: 1 Gerrit-Owner: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 09:30:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: soc/riscv/ucb: Switch to FDT parsing to get memory size
by Carlos López (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Joel Bueno, Philipp Hug, ron minnich. Carlos López has posted comments on this change by Joel Bueno. ( https://review.coreboot.org/c/coreboot/+/86588?usp=email ) Change subject: soc/riscv/ucb: Switch to FDT parsing to get memory size ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43 Gerrit-Change-Number: 86588 Gerrit-PatchSet: 3 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 09:25:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: commonlib/device_tree: fix 64-bit misaligned member access
by Carlos López (Code Review) 25 Feb '25

25 Feb '25

Attention is currently required from: Joel Bueno, Julius Werner, Maximilian Brune, Philipp Hug, ron minnich. Carlos López has posted comments on this change by Joel Bueno. ( https://review.coreboot.org/c/coreboot/+/85800?usp=email ) Change subject: commonlib/device_tree: fix 64-bit misaligned member access ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Reviewer: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Joel Bueno <joel.bueno(a)openchip.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 25 Feb 2025 09:23:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025