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Change subject: mb/google/fatcat: Set frequency and gears for SaGv work points
......................................................................
mb/google/fatcat: Set frequency and gears for SaGv work points
Update sagv gears and frequency values as per recommendation
from power and performance team.
BUG=b:none
TEST=Boot to OS.
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: I315fcac387680df9312880120b7e6d33bded38e0
---
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/86274/2
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Change subject: drivers/intel/gma: Fix alignment of extended VBT in opregion
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/86275/comment/09a3f7dc_58f70a5c?us… :
PS1, Line 337: opregion_size += ext_vbt_size;
Could you use a macro such as `ALIGN_UP` ?
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Change subject: mb/google/fatcat: Set frequency and gears for sagv points
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
......................................................................
Patch Set 15:
(1 comment)
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85454/comment/c9fb0def_8f1ea81d?us… :
PS11, Line 375:
> This is not supported in the current design. I raised the point in December.
Please read my previous message as `CSE sync at ramstage` like what we did in MTL.
> I requested a mechanism for the bootloader (coreboot) to control VGA exit. Once available, I will push a new CL and update this function.
We should avoid tearing down the uGOP if CSE update is due. And CSE update can still show the VGA test msg. In case no CSE sync is pending, we can skip rendering CSE sync. due to CSE sync at pre-boot phase, we might not be able to check if CSE is booting from RO or RW (is_cse_boot_to_rw) as decision point to avoid tearing down of the uGOP eSOL like we did in MTL.
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Attention is currently required from: Alok Agarwal, Bora Guvendik, Cliff Huang, Intel coreboot Reviewers, Jamie Ryu, Ronak Kanabar, Subrata Banik, Zhixing Ma.
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I'd like you to reexamine a change. Please visit
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Change subject: vc/intel/fsp: Update PTL FSP headers to 3015.00
......................................................................
vc/intel/fsp: Update PTL FSP headers to 3015.00
This update revises the Panther Lake Firmware Support Package (FSP)
headers to incorporate the latest enhancements for Panther Lake FSP
version 3015.00. Modifications are made to the FspmUpd.h and FspsUpd.h
header files to integrate these advancements.
The update introduces the following significant alterations:
- Introduction of settings to manage the Intel Total Memory Encryption
(TME) feature.
- A feature designed to reduce acoustic noise emissions for specific
product models when the CPU operates in an advanced C power-saving
state.
- Implementation of PSYS PMax power adjustments.
- Adjustments to the AcLoadline and DcLoadline parameters.
- The inclusion of FastPkgCRampDisable, which controls the Fast Slew
Rate for Voltage Regulator (VR) domains when in Deep Package C
States, aiding in the reduction of acoustic noise during these
states.
- A new limit setting for the Voltage Regulator Fast Voltage Mode
(Vmode) inrush current (ICC).
- A toggle for the activation or deactivation of Current Excursion
Protection (CEP).
- VgaInitControl, a directive to initialize the VGA based
sign-of-life.
TEST: google/fatcat build can be successfully compiled.
Change-Id: I1b43faa704959dce5846e22e57f81e651be2d56c
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
2 files changed, 1,243 insertions(+), 1,086 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/86258/2
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Change subject: soc/amd/common: Support sbin ucode files
......................................................................
Patch Set 10: Code-Review+1
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Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
......................................................................
Patch Set 21:
(1 comment)
File src/drivers/amd/opensil/memmap.c:
https://review.coreboot.org/c/coreboot/+/85634/comment/61a7300a_b7f4b079?us… :
PS20, Line 36: if (top_of_mem <= 4ULL * GiB)
> this check needs to be after the opensil_get_hole_info call; right now this is always true. […]
Done
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Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
......................................................................
drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
Refactor the vendercode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.
Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com>
---
M src/drivers/amd/opensil/Makefile.mk
A src/drivers/amd/opensil/memmap.c
M src/drivers/amd/opensil/opensil.h
M src/soc/amd/genoa_poc/domain.c
M src/soc/amd/phoenix/memmap.c
M src/vendorcode/amd/opensil/genoa_poc/memmap.c
M src/vendorcode/amd/opensil/opensil.h
M src/vendorcode/amd/opensil/stub/ramstage.c
8 files changed, 124 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85634/21
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