coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: mb/google/fatcat: Use early power off support
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86359?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Use early power off support ...................................................................... mb/google/fatcat: Use early power off support This commit selects `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig that allows the platform to perform early power off procedures, which are often required on Intel platforms to implement eSOL (early Sign-Of-Life) during low-battery boot. BUG=b:339673254 TEST=Able to build and boot google/fatcat. Change-Id: Id6b31d6916898541b0396002376910eed5d26b06 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/86359/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6b31d6916898541b0396002376910eed5d26b06 Gerrit-Change-Number: 86359 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox: Use early power off support
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86356?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Use early power off support ...................................................................... mb/google/brox: Use early power off support This commit selects `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig that allows the platform to perform early power off procedures, which are often required on Intel platforms to implement eSOL (early Sign-Of-Life) during low-battery boot. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: Ib748cb4d540c631afd0f6bd5bff23ec17601f3ed Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/86356/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib748cb4d540c631afd0f6bd5bff23ec17601f3ed Gerrit-Change-Number: 86356 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/meliks: Update GPIO configuration
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

1 0

[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Update overridetree.cb
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Update overridetree.cb ...................................................................... mb/google/nissa/var/meliks: Update overridetree.cb Upload the initial devicetree for meliks. All devices and port usages are the same as pirrha, just copied from pirrha's devicetree for the initial configuration. BUG=b:394359785 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/meliks/overridetree.cb 1 file changed, 508 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/86377/1 diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb index 4f2c04a..ffc51cc 100644 --- a/src/mainboard/google/brya/variants/meliks/overridetree.cb +++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb @@ -1,6 +1,512 @@ chip soc/intel/alderlake + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_C" - device domain 0 on - end + # Enable MIPI DSI on DDI port A + register "ddi_portA_config" = "2" # MIPI DSI + register "sagv" = "SaGv_Enabled" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_11P25MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + .type_c = 1, + }" # USB2_C1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_11P25MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # USB2_A0 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .pre_emp_bias = USB2_BIAS_28P15MV, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # uSD + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, + }" # UFCamera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX , + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX , + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + # VR Settings + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .vr_config_enable = 1, + .tdc_timewindow = 1000, + .ac_loadline = 500, + .dc_loadline = 500, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + }" + + register "domain_vr_config[VR_DOMAIN_GT]" = "{ + .vr_config_enable = 1, + .tdc_timewindow = 1000, + .psi1threshold = VR_CFG_AMP(13), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | WCAM | + #| I2C3 | Audio | + #| I2C4 | EMR | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .panel_orientation = LB_FB_ORIENTATION_RIGHT_UP, + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Sub Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1, + .time_window_max = 1, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""HX121A"" + register "generic.desc" = ""HX Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.reset_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x4F on end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "true" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "btn_cfg" = "50" + register "mic_det_thr" = "200" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM014B"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_F12)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "generic.reset_delay_ms" = "100" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x09 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "da7219" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + device ref pcie_rp7 off end + device ref pcie_rp9 off end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/meliks: Update memory DQ/DQS map
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/meliks: Generate SPD ID for supported parts
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/meliks: Update Kconfig for meliks
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

1 0

[S] Change in coreboot[main]: mb/google/nissa: Create meliks variant
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86373?usp=email ) Change subject: mb/google/nissa: Create meliks variant ...................................................................... mb/google/nissa: Create meliks variant Create the meliks variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:394359785 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MELIKS Change-Id: Iff5e27ef06a44976c2724751de0f9c6d5cf6eaaf Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/meliks/include/variant/ec.h A src/mainboard/google/brya/variants/meliks/include/variant/gpio.h A src/mainboard/google/brya/variants/meliks/memory/Makefile.mk A src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/meliks/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86373/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 58b8922..973c5d7 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -979,6 +979,7 @@ default "Pujjoga" if BOARD_GOOGLE_PUJJOGA default "Telith" if BOARD_GOOGLE_TELITH default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN + default "Meliks" if BOARD_GOOGLE_MELIKS config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -1053,6 +1054,7 @@ default "pujjoga" if BOARD_GOOGLE_PUJJOGA default "telith" if BOARD_GOOGLE_TELITH default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN + default "meliks" if BOARD_GOOGLE_MELIKS config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 50bfaef..ba1aea3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -217,3 +217,7 @@ config BOARD_GOOGLE_TELITH bool "-> Telith" + +config BOARD_GOOGLE_MELIKS + bool "-> Meliks" + select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/ec.h b/src/mainboard/google/brya/variants/meliks/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/meliks/overridetree.cb b/src/mainboard/google/brya/variants/meliks/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/meliks/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/86373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff5e27ef06a44976c2724751de0f9c6d5cf6eaaf Gerrit-Change-Number: 86373 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... Patch Set 13: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/86225/comment/2902e5ae_d0604927?us… : PS13, Line 535: config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR > Actually, I'm not really sure anymore why this option exists and why mainboards should select it. Why would a mainboard ever not want to select this if the dependencies are there? Why don't we just make `PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR` `depends on PLATFORM_HAS_LOW_BATTERY_INDICATOR && (FSP_UGOP_EARLY_SIGN_OF_LIFE || MAINBOARD_HAS_EARLY_LIBGFXINIT)` directly? There are two reasons to keep the control inside mainboard 1. Allow rendering low-battery shutdown msg is a platform choice, so we can;t force a platform to show the eSOL msg or UI msg depending upon mainboard supports uGOP/libgfxinit 2. low battery rendering would use a portion of eSOL technology. take a case for PTL, where eSOL feature is ready but not low-battery handing inside uGOP therefore, we can't enforce to enable this feature if platform supports either uGOP or libgfxinit > > (But then again, `FSP_UGOP_EARLY_SIGN_OF_LIFE` and `MAINBOARD_HAS_EARLY_LIBGFXINIT` only determine whether the platform has the ability to show an early update message, but it doesn't say whether that message is actually enabled. But if it is not enabled, there's no point in enabling the early low battery screen. So should we maybe depend in `CHROMEOS_ENABLE_ESOL` instead, because that's actually the option that turns the early message on. But why is that even a `CHROMEOS` option? Shouldn't that be more generalized, either in `src/soc/intel/common` or in the toplevel Kconfig?) To maintain platform independence from ChromeOS, this feature allows overrides for configurable parameters like APIs for logo display, text messages, poweroff control, and low-battery indicators. Platforms can implement these APIs as needed. The underlying technology leverages FSP logo rendering for UI and eSOL VGA for early text display. I don't think there is any need to draw CrOS dependency here. At this point, we have only two possible ways to render eSOL, either libgfx or uGOP. -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 10:11:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Bora Guvendik, Zhixing Ma. Subrata Banik has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email ) Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85960/comment/15e92dd8_7cc27a25?us… : PS5, Line 16: > Hi Subrata, > Here is the dmidecode output with and without this patch, as well as a comparison to MTL platform (rex): > without patch: > ``` > Handle 0x0004, DMI type 4, 48 bytes > Processor Information > Socket Designation: CPU0 > Type: Central Processor > Family: Pentium Pro > Manufacturer: GenuineIntel > ID: C0 06 0C 00 FF FB EB BF > Signature: Type 0, Family 6, Model 204, Stepping 0 > Flags: ... > Version: Genuine Intel(R) 0000 > Voltage: Unknown > External Clock: 100 MHz > Max Speed: 3200 MHz > Current Speed: 3000 MHz > Status: Populated, Enabled > Upgrade: Unknown > ``` > with patch: > ``` > Handle 0x0004, DMI type 4, 48 bytes > Processor Information > Socket Designation: CPU0 > Type: Central Processor > Family: Pentium Pro > Manufacturer: GenuineIntel > ID: C0 06 0C 00 FF FB EB BF > Signature: Type 0, Family 6, Model 204, Stepping 0 > Flags: ... > Version: Genuine Intel(R) 0000 > Voltage: Unknown > External Clock: 100 MHz > Max Speed: 3200 MHz > Current Speed: 3000 MHz > Status: Populated, Enabled > Upgrade: Other > ``` > on rex: > ``` > Handle 0x0004, DMI type 4, 48 bytes > Processor Information > Socket Designation: CPU0 > Type: Central Processor > Family: Pentium Pro > Manufacturer: GenuineIntel > ID: A4 06 0A 00 FF FB EB BF > Signature: Type 0, Family 6, Model 170, Stepping 4 > Flags: ... > Version: Genuine Intel(R) 0000 > Voltage: 1.2 V > External Clock: 100 MHz > Max Speed: 4900 MHz > Current Speed: 2700 MHz > Status: Populated, Enabled > Upgrade: Other > ... > ``` thanks, can you please add w/ and w/o patch details in the commit msg ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 5 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 09:37:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhixing Ma <zhixing.ma(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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