coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Angel Pons (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, David Hendricks. Angel Pons has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/86131/comment/dfbc15fd_09c2dc2a?us… : PS6, Line 1013: bool "Extend resource window for PCIe devices above 4G" As per our discussion with Arthur, showing the prompt on non-x86 doesn't make much sense. How about: ```suggestion bool prompt "Extend resource window for PCIe devices above 4G" if ARCH_X86 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 6 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 12 Feb 2025 10:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/meliks: Update Kconfig for meliks
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

SH Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86374?usp=email ) Change subject: mb/google/nissa/var/meliks: Update Kconfig for meliks ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fc318276c50bedb57f1559107ad60eafbd1f3a9 Gerrit-Change-Number: 86374 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common: Add low battery shutdown function
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86361?usp=email ) Change subject: soc/intel/common: Add low battery shutdown function ...................................................................... Patch Set 3: (1 comment) File src/include/reset.h: https://review.coreboot.org/c/coreboot/+/86361/comment/2ccf3d39_73282fb8?us… : PS3, Line 51: * 2. Introduces a short delay to allow time for logging. > I think the time is really to allow the user to see the low battery screen (and the comment here sho […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86361?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4 Gerrit-Change-Number: 86361 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 10:46:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0
by Jarried Lin (Code Review) 12 Feb '25

12 Feb '25

Jarried Lin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/blobs/+/86380?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 Update mtk_fsp_ramstage.elf includes: - Disable clock for Crypto hardware. - Add build version info. BRANCH=rauru TEST=Build pass BUG=b:317009620 Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 4 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/86380/2 -- To view, visit https://review.coreboot.org/c/blobs/+/86380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Gerrit-Change-Number: 86380 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0
by Jarried Lin (Code Review) 12 Feb '25

12 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86380?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 ...................................................................... soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 Update mtk_fsp_ramstage.elf includes: - Disable clock for Crypto hardware. - Add build version info. BRANCH=rauru TEST=Build pass BUG=b:317009620 Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md M soc/mediatek/mt8196/mtk_fsp_ramstage.elf M soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 M soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt 4 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/86380/1 diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 4f5ee64..b9aec8f 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -266,6 +266,7 @@ - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. +- Disable clock for Crypto hardware. ## Who uses it Coreboot loads `mtk_fsp_ramstage.elf` during the first bootup. @@ -279,6 +280,6 @@ 0 on success; non-zero on failure. ## Version -`$ strings mtk_fsp_ramstage.elf | grep "interface version"` +`$ strings mtk_fsp_ramstage.elf | grep "build version"` -------------------------------------------------------------------------------- diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf old mode 100644 new mode 100755 index 783eb66..6958e03 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf Binary files differ diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 index 3e6085f..841ba24 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage.elf.md5 @@ -1 +1 @@ -3b4068efe7b6c5aebc2379985c5316e4 *mtk_fsp_ramstage.elf +acea3c8559c673529bfb1261404c4bd5 *mtk_fsp_ramstage.elf diff --git a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt index b63d1e6..1f5d730 100644 --- a/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt +++ b/soc/mediatek/mt8196/mtk_fsp_ramstage_release_notes.txt @@ -1,3 +1,13 @@ +# 16189.0.0 + +1. An official build from ChromeOS version 16189.0.0. + +2. Include changes: + +- CL:*7980492 mt8196/kraken_v3: Call dsb() after writing to CSRAM +- CL:*8009008 mt8196: Disable clock for Crypto hardware +- CL:*8013108 mtk-fsp: Add build version info + # 1.0 1. An official build from ChromeOS version 16180.0.0. -- To view, visit https://review.coreboot.org/c/blobs/+/86380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Gerrit-Change-Number: 86380 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/meliks: Update GPIO configuration
by SH Kim (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86378?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/meliks: Update GPIO configuration ...................................................................... mb/google/nissa/var/meliks: Update GPIO configuration Update the initial GPIO configuration for meliks by referring to the schematics. BUG=b:394359785 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: I33e1e3be5f2530feb396e7413f3f0cd75d5f38ca Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/meliks/Makefile.mk A src/mainboard/google/brya/variants/meliks/gpio.c M src/mainboard/google/brya/variants/meliks/include/variant/gpio.h 3 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/86378/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86378?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33e1e3be5f2530feb396e7413f3f0cd75d5f38ca Gerrit-Change-Number: 86378 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: amdfwtool: Move ISH before PSP L2
by Bao Zheng (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Maximilian Brune, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84533?usp=email ) Change subject: amdfwtool: Move ISH before PSP L2 ...................................................................... Patch Set 12: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84533/comment/6887f3bb_95a4c0a2?us… : PS12, Line 972: if (!cb_config->combo_new_rab || ctx->combo_index == 0) { : pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); : ctx->pspdir = pspdir; : if (recovery_ab) : ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie); : } : /* The ISH tables are with PSP L1. */ : if (cb_config->need_ish && ctx->ish_a_dir == NULL) /* Need ISH */ : ctx->ish_a_dir = new_ish_dir(ctx); : if (cb_config->need_ish && ctx->ish_b_dir == NULL) /* Need ISH */ : ctx->ish_b_dir = new_ish_dir(ctx); > What happens if `combo_new_rab = 0` and `recovery_ab = 1` ? In that case no PSP L1 directory is crea […] For the family older than mendocino, it uses the old combo definition. There is a combo header, which points to multiple PL1. For the newer family, it only has one PL1, which points to multiple ISH(es). If it is in first iteration (for non-combo case, which is the only iteration), it creates the PL1. For the second iteration, old combo still needs a PL1. Other cases PL1 is not needed. "new combo" is not mentioned in the spec yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/84533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Gerrit-Change-Number: 84533 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Feb 2025 10:40:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/86336/comment/cc2341a7_7961d1bc?us… : PS6, Line 314: #if CONFIG(HAVE_EARLY_POWEROFF_SUPPORT) > This is unnecessary because the function will never get called when the Kconfig is off anyway. Acknowledged File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/86336/comment/17645c5b_b4e8d028?us… : PS6, Line 12: #include <ec/google/chromeec/ec.h> > It should not be needed anymore. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 10:38:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: ec/google/chromeec: Add early power off support
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86379?usp=email ) Change subject: ec/google/chromeec: Add early power off support ...................................................................... ec/google/chromeec: Add early power off support This commit adds support for early power off on Intel SoC platforms. It introduces a platform_do_early_poweroff() function which, when HAVE_EARLY_POWEROFF_SUPPORT is enabled, calls the EC's early power off function (google_chromeec_do_early_powerof()). Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/Makefile.mk A src/ec/google/chromeec/reset.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/86379/1 diff --git a/src/ec/google/chromeec/Makefile.mk b/src/ec/google/chromeec/Makefile.mk index 6465c2c..c8ebe57 100644 --- a/src/ec/google/chromeec/Makefile.mk +++ b/src/ec/google/chromeec/Makefile.mk @@ -40,6 +40,8 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c +romstage-$(CONFIG_HAVE_EARLY_POWEROFF_SUPPORT) += reset.c + ramstage-$(CONFIG_VBOOT) += vboot_storage.c smm-$(CONFIG_VBOOT) += vboot_storage.c romstage-$(CONFIG_VBOOT) += vboot_storage.c diff --git a/src/ec/google/chromeec/reset.c b/src/ec/google/chromeec/reset.c new file mode 100644 index 0000000..eefaef5 --- /dev/null +++ b/src/ec/google/chromeec/reset.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <intelblocks/pmclib.h> + +void platform_do_early_poweroff(void) +{ + google_chromeec_do_early_poweroff(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff Gerrit-Change-Number: 86379 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Subrata Banik. Hello Angel Pons, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86336?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Julius Werner, Code-Review+2 by Karthik Ramasubramanian, Verified+1 by build bot (Jenkins) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... soc/intel/cmn/pmc: Add support for early power off This commit adds support for early power off on Intel platforms along with existing PMC based implementation to support power off at later stage (like ramstage). A new function, `platform_do_early_poweroff`, is added to the pmclib to handle platform-specific early power off procedures. This function is called before memory initialization (in romstage or earlier). Platform that supports early power off (using HAVE_EARLY_POWEROFF_SUPPORT Kconfig) needs to implement `platform_do_early_poweroff()` to power off the platform. Note: While Intel chipsets do not support power off before silicon initialization, this change leverages Chrome EC APIs to enable power off in romstage for low-battery boot on ChromeOS devices. Power off failures in ramstage prior to FSP-S are outside the scope of this change. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c 3 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86336/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit February 2025