coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/amd/common/block/graphics: Support non VGA IGDs
by Patrick Rudolph (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86300?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/block/graphics: Support non VGA IGDs ...................................................................... soc/amd/common/block/graphics: Support non VGA IGDs On glinda the IGD is no longer VGA compatible. It doesn't advertise itself as a VGA compatible devices and doesn't decode the legacy VGA ranges 0x3C0-0x3CF, 0x3D4. Introduce a new Kconfig and select it where necessary to keep existing behaviour on older SoC while fixing FSP GOP init on glinda. The VBIOS will get loaded into the D-segment instead the C-segment, which is typically used by VGA. TEST: FSP GOP on amd/birman+ is able to find the VBIOS. amdgpu driver still doesn't work as the VFCT table isn't generated on amd/glinda. Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/amd/common/block/graphics/Kconfig M src/soc/amd/common/block/graphics/graphics.c M src/soc/amd/glinda/Kconfig 3 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86300/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88 Gerrit-Change-Number: 86300 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns
by Yu-Ping Wu (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86371?usp=email ) Change subject: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Gerrit-Change-Number: 86371 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 14:55:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs
by Krystian Hebel (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Filip Lewiński, Michał Kopeć, Michał Żygowski, Paul Menzel. Krystian Hebel has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83727?usp=email ) Change subject: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/cannonlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/83727/comment/08664faa_159bd733?us… : PS3, Line 152: m_cfg->ApStartupBase = 1; /* Set to non-zero, FSP does NULL check */ Doesn't this cause APs to eventually jump to address 1 and (most likely) hit an exception at some point because there is no valid code at that address? With regard to CB:82697, this may put APs in a state from which they can't be brought back to do other tasks (e.g. shutdown after a triple-fault). Wouldn't it be better to end the execution with something like `stop_this_cpu()` instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/83727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibca1c7c8a5335dab8af4888aee4c60683b72746d Gerrit-Change-Number: 83727 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-CC: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 12 Feb 2025 14:53:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add libbl31.a version v1.0
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Gavin Liu, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Gavin Liu. ( https://review.coreboot.org/c/blobs/+/86382?usp=email ) Change subject: soc/mediatek/mt8196: Add libbl31.a version v1.0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @jarried.lin@mediatek.com Can you review this patch first ? -- To view, visit https://review.coreboot.org/c/blobs/+/86382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Gerrit-Change-Number: 86382 Gerrit-PatchSet: 2 Gerrit-Owner: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 14:25:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add libbl31.a version v1.0
by Gavin Liu (Code Review) 12 Feb '25

12 Feb '25

Gavin Liu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/blobs/+/86382?usp=email ) Change subject: soc/mediatek/mt8196: Add libbl31.a version v1.0 ...................................................................... soc/mediatek/mt8196: Add libbl31.a version v1.0 The static library that contains Mediatek private drivers in ARM-Trusted-Firmware: - UFS driver - SMPU (Security Memory Protection Unit) driver - SLBC driver - CPU QOS driver - mminfra driver - smmu_sid driver BRANCH=rauru BUG=b:317009620 TEST=Build pass with static library. Boot ok. Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Signed-off-by: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/libbl31.a A soc/mediatek/mt8196/libbl31.a.md5 A soc/mediatek/mt8196/libbl31_release_note.txt 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/82/86382/2 -- To view, visit https://review.coreboot.org/c/blobs/+/86382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Gerrit-Change-Number: 86382 Gerrit-PatchSet: 2 Gerrit-Owner: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add libbl31.a version v1.0
by Gavin Liu (Code Review) 12 Feb '25

12 Feb '25

Gavin Liu has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86382?usp=email ) Change subject: soc/mediatek/mt8196: Add libbl31.a version v1.0 ...................................................................... soc/mediatek/mt8196: Add libbl31.a version v1.0 The static library that contains Mediatek private drivers in ARM-Trusted-Firmware: - UFS driver - SMPU (Security Memory Protection Unit) driver - SLBC driver - CPU QOS driver - mminfra driver - smmu_sid driver BRANCH=rauru BUG=b:373797027 TEST=Build pass with static library. Boot ok. Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Signed-off-by: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/libbl31.a A soc/mediatek/mt8196/libbl31.a.md5 A soc/mediatek/mt8196/libbl31_release_note.txt 4 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/82/86382/1 diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 4f5ee64..a0db757 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -9,6 +9,7 @@ - pi_img.img - mtk_fsp_romstage.elf - mtk_fsp_ramstage.elf +- libbl31.a -------------------------------------------------------------------------------- # MCUPM introduction @@ -282,3 +283,16 @@ `$ strings mtk_fsp_ramstage.elf | grep "interface version"` -------------------------------------------------------------------------------- +# libbl31.a introduction +It is a static library that contains Mediatek private drivers in ARM-Trusted-Firmware such as: + +- UFS driver +- SMPU (Security Memory Protection Unit) driver +- SLBC driver +- CPU QOS driver +- mminfra driver +- smmu_sid driver + +## Who use it +ARM-Trusted-Firmware links `libbl31.a` when building `bl31.elf`. + diff --git a/soc/mediatek/mt8196/libbl31.a b/soc/mediatek/mt8196/libbl31.a new file mode 100755 index 0000000..f758652 --- /dev/null +++ b/soc/mediatek/mt8196/libbl31.a Binary files differ diff --git a/soc/mediatek/mt8196/libbl31.a.md5 b/soc/mediatek/mt8196/libbl31.a.md5 new file mode 100644 index 0000000..130f403 --- /dev/null +++ b/soc/mediatek/mt8196/libbl31.a.md5 @@ -0,0 +1,2 @@ +0316f5be548efda05e915d2cd7d0f179 *libbl31.a + diff --git a/soc/mediatek/mt8196/libbl31_release_note.txt b/soc/mediatek/mt8196/libbl31_release_note.txt new file mode 100644 index 0000000..8b474fe --- /dev/null +++ b/soc/mediatek/mt8196/libbl31_release_note.txt @@ -0,0 +1,11 @@ +# 1.0 + +1. An official build from ChromeOS version + +2. Include driver patches: + +- CL:*8004008 feat(mt8196): add MT8196 UFS driver +- CL:*8004009 feat(mt8196): add MT8196 SMPU driver +- CL:*8004010 feat(mt8196): add MT8196 slbc and cpu_qos drivers +- CL:*8004011 feat(mt8196): add mminfra and smmu_sid drivers +- CL:*8020869 CHROMIUM: fix(mt8196): remove duplicate mapping from smmu_sid -- To view, visit https://review.coreboot.org/c/blobs/+/86382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ided5b662464be64cb8d9db938eb513ac7b1d6e18 Gerrit-Change-Number: 86382 Gerrit-PatchSet: 1 Gerrit-Owner: Gavin Liu <gavin.liu(a)mediatek.corp-partner.google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86380?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to version: 16189.0.0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/86380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Gerrit-Change-Number: 86380 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 13:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Add EC suspend pin initial setting
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email ) Change subject: mb/google/rauru: Add EC suspend pin initial setting ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86381/comment/aac20048_7eee5039?us… : PS3, Line 7: mb/google/rauru: Add EC suspend pin initial setting : : Set the EC suspend pin to output high. Please revise the commit message. And the purpose of the setting. File src/mainboard/google/rauru/gpio.h: https://review.coreboot.org/c/coreboot/+/86381/comment/84fca492_43cfb7f5?us… : PS3, Line 17: GPIO_EC_SUSPEND_PIN `GPIO_AP_SUSPEND_L`. Please always follow the naming on the schematic. -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 12:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86371?usp=email ) Change subject: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Gerrit-Change-Number: 86371 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2025 12:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns
by Jarried Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86371?usp=email to look at the new patch set (#4). Change subject: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns ...................................................................... soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns. Additionally, a hardware solution of SPMI damping to 0 ohm is needed. BRANCH=rauru TEST=Build passed and booted successfully. 10 platforms have passed CPU stress tests over multiple iterations. BUG=b:386438329 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 --- M src/soc/mediatek/common/include/soc/mt6316.h M src/soc/mediatek/common/mt6316.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86371/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Gerrit-Change-Number: 86371 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit February 2025