coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns
by Jarried Lin (Code Review) 11 Feb '25

11 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86371?usp=email ) Change subject: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns ...................................................................... soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns. Additionally, a hardware solution of SPMI damping to 0 ohm is needed. TEST=Build passed and booted … [View More]successfully. 10 platforms have passed over two days. BUG=b:386438329 BRANCH=rauru Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 --- M src/soc/mediatek/common/include/soc/mt6316.h M src/soc/mediatek/common/mt6316.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/86371/1 diff --git a/src/soc/mediatek/common/include/soc/mt6316.h b/src/soc/mediatek/common/include/soc/mt6316.h index 920cb34..2e26805 100644 --- a/src/soc/mediatek/common/include/soc/mt6316.h +++ b/src/soc/mediatek/common/include/soc/mt6316.h @@ -29,6 +29,7 @@ MT6316_PMIC_TEST_CON9 = 0x222, MT6316_PMIC_PLT_DIG_WPK = 0x3B1, MT6316_PMIC_PLT_DIG_WPK_H = 0x3B2, + MT6316_PMIC_RG_SPMI_RSV1_ADDR = 0x43A, MT6316_BUCK_TOP_ELR0 = 0x1448, MT6316_BUCK_TOP_ELR1 = 0x1449, MT6316_BUCK_TOP_ELR2 = 0x144A, diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c index 89c8c83..6fc0201 100644 --- a/src/soc/mediatek/common/mt6316.c +++ b/src/soc/mediatek/common/mt6316.c @@ -169,6 +169,14 @@ mt6316_write8(mt6316_slave_id[i], MT6316_PMIC_TEST_CON9, 0x20); } +static void mt6316_set_all_deglitch(void) +{ + /* Set deglitch time from 2ns to 4ns */ + for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) + mt6316_write_field(mt6316_slave_id[i], + MT6316_PMIC_RG_SPMI_RSV1_ADDR, 0xA, 0xFF, 0); +} + static void init_pmif_arb(void) { if (pmif_arb) @@ -196,4 +204,5 @@ mt6316_init_setting(); mt6316_set_all_test_con9(); + mt6316_set_all_deglitch(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Gerrit-Change-Number: 86371 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> [View Less]

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[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3
by Dtrain Hsu (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86362?usp=email ) Change subject: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86362?… [View More]

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports
by Matt DeVillier (Code Review) 11 Feb '25

11 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86338?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports ...................................................................... mb/google/trulo/var/uldrenite: Add fw_config probe for USB-C ports Use fw_config to probe USB-C ports. BUG=b:392040004 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: … [View More]Ic0161e8b85c5a2afe6ec8473497d21a5737f4f70 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86338 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 10 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 862968e..285db4a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -7,6 +7,10 @@ option TOUCHSCREEN_UNKNOWN 0 option TOUCHSCREEN_NONE 1 end + field MB_TYPEC 7 7 + option MB_C_TWO 0 + option MB_C_ONE 1 + end end chip soc/intel/alderlake @@ -250,7 +254,9 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port2 on + probe MB_TYPEC MB_C_TWO + end end end end @@ -270,7 +276,9 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end + device ref usb2_port2 on + probe MB_TYPEC MB_C_TWO + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" -- To view, visit https://review.coreboot.org/c/coreboot/+/86338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0161e8b85c5a2afe6ec8473497d21a5737f4f70 Gerrit-Change-Number: 86338 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> [View Less]

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Support x32 memory configuration
by John Su (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86364?usp=email to look at the new patch set (#4). Change subject: mb/trulo/var/uldrenite: Support x32 memory configuration ..............................................… [View More]........................ mb/trulo/var/uldrenite: Support x32 memory configuration Use the GPP_E13 level to determine whether x32 memory configuration is supported. BUG=b:379311559 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/memory.c 3 files changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86364/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Gerrit-Change-Number: 86364 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> [View Less]

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[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3
by John Su (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86362?usp=email ) Change subject: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3 ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/uldrenite/gpio.c: https://… [View More]

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Support x32 memory configuration
by John Su (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86364?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/trulo/var/… [View More]uldrenite: Support x32 memory configuration ...................................................................... mb/trulo/var/uldrenite: Support x32 memory configuration Use the GPP_E13 level to determine whether x32 memory configuration is supported. BUG=b:379311559 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/memory.c 3 files changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86364/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Gerrit-Change-Number: 86364 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> [View Less]

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[XS] Change in coreboot[main]: Update blobs submodule to upstream main
by Yu-Ping Wu (Code Review) 11 Feb '25

11 Feb '25

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86365?usp=email ) Change subject: Update blobs submodule to upstream main ...................................................................... Update blobs submodule to upstream main Updating from commit id 14f8fcc1b426: 2024-11-28 05:07:49 +0000 - (soc/mediatek/mt8196: Update SSPM firmware to v2.0) to commit id a0726508b86d: 2025-02-06 17:31:46 +0800 - (soc/mediatek/mt8196: Update SSPM firmware to v4.0) … [View More]

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[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3
by John Su (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86362?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/trulo/var/… [View More]uldrenite: Remove GPP_E13 from being used as RAM ID3 ...................................................................... mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3 Remove GPP_E13 from being used as RAM ID3. Planned to be used as a strap pin to disable memory channels for x32 memory configuration. BUG=b:379311559 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/memory.c 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/86362/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33 Gerrit-Change-Number: 86362 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> [View Less]

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[M] Change in coreboot[main]: haswell NRI: Add range tracking library
by Alicja Michalska (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Alicja Michalska has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/64192?usp=email ) Change subject: haswell NRI: Add range tracking library ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64192?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

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[XL] Change in coreboot[main]: haswell NRI: Add REUT I/O test library
by Alicja Michalska (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber. Alicja Michalska has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/64191?usp=email ) Change subject: haswell NRI: Add REUT I/O test library ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64191?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

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coreboot-gerrit February 2025