coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Maximilian Brune (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Alicja Michalska, Ana Carolina Cabral, Felix Held, Matt DeVillier, Paul Menzel. Hello Alicja Michalska, Ana Carolina Cabral, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84500?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... mb/amd/birman_plus: Update devicetree The devicetree was still a copy of a previous mainboard. This patch updates the devicetree for the birman_plus mainboard. Birman plus is an AMD reference board. sources: - document #58168 Rev 1.01 "Birman+ User Guide" - birman+ schematic Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/devicetree_glinda.cb 2 files changed, 43 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84500/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Maximilian Brune (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Alicja Michalska, Ana Carolina Cabral, Felix Held, Matt DeVillier, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84500?usp=email ) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... Patch Set 5: (1 comment) File src/mainboard/amd/birman_plus/devicetree_glinda.cb: https://review.coreboot.org/c/coreboot/+/84500/comment/0aef1bd2_e08529b5?us… : PS4, Line 192: device ref gpp_bridge_2_4 on end # GBE > gpp_bridge_2_5 (wwan), gpp_bridge_3_1 (mxm; probably rather a pcie slot though), and gpp_bridge_3_2 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Feb 2025 14:51:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update devicetree
by Maximilian Brune (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Alicja Michalska, Ana Carolina Cabral, Matt DeVillier, Maximilian Brune, Paul Menzel. Hello Alicja Michalska, Ana Carolina Cabral, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84500?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Alicja Michalska, Code-Review+1 by Paul Menzel, Code-Review+2 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: mb/amd/birman_plus: Update devicetree ...................................................................... mb/amd/birman_plus: Update devicetree The devicetree was still a copy of a previous mainboard. This patch updates the devicetree for the birman_plus mainboard. Birman plus is an AMD reference board. sources: - document #58168 Rev 1.01 "Birman+ User Guide" - birman+ schematic Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/devicetree_glinda.cb 2 files changed, 43 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84500/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cc2e4c8f722048b24d84cf782855ae7a8d64c42 Gerrit-Change-Number: 84500 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns
by Yidi Lin (Code Review) 13 Feb '25

13 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86371?usp=email ) Change subject: soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns ...................................................................... soc/mediatek/mt8196: Set MT6316 deglitch time from 2ns to 4ns To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns. Additionally, a hardware solution of SPMI damping to 0 ohm is needed. BRANCH=rauru TEST=Build passed and booted successfully. 10 platforms have passed CPU stress tests over multiple iterations. BUG=b:386438329 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86371 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Knox Chiou <knoxchiou(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/common/include/soc/mt6316.h M src/soc/mediatek/common/mt6316.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Knox Chiou: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6316.h b/src/soc/mediatek/common/include/soc/mt6316.h index 920cb34..ce955f9 100644 --- a/src/soc/mediatek/common/include/soc/mt6316.h +++ b/src/soc/mediatek/common/include/soc/mt6316.h @@ -29,6 +29,7 @@ MT6316_PMIC_TEST_CON9 = 0x222, MT6316_PMIC_PLT_DIG_WPK = 0x3B1, MT6316_PMIC_PLT_DIG_WPK_H = 0x3B2, + MT6316_PMIC_SPMI_RSV1 = 0x43A, MT6316_BUCK_TOP_ELR0 = 0x1448, MT6316_BUCK_TOP_ELR1 = 0x1449, MT6316_BUCK_TOP_ELR2 = 0x144A, diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c index 89c8c83..9ed5d29 100644 --- a/src/soc/mediatek/common/mt6316.c +++ b/src/soc/mediatek/common/mt6316.c @@ -169,6 +169,14 @@ mt6316_write8(mt6316_slave_id[i], MT6316_PMIC_TEST_CON9, 0x20); } +static void mt6316_set_all_deglitch(void) +{ + /* Set deglitch time from 2ns to 4ns */ + for (int i = 0; i < ARRAY_SIZE(mt6316_slave_id); i++) + mt6316_write_field(mt6316_slave_id[i], + MT6316_PMIC_SPMI_RSV1, 0x0A, 0xFF, 0); +} + static void init_pmif_arb(void) { if (pmif_arb) @@ -196,4 +204,5 @@ mt6316_init_setting(); mt6316_set_all_test_con9(); + mt6316_set_all_deglitch(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86 Gerrit-Change-Number: 86371 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.22.0
by Yidi Lin (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86380?usp=email ) Change subject: soc/mediatek/mt8196: update mtk_fsp_ramstage to 16174.22.0 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/86380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic785a04e576065a250f55a78105abf42b61a15a7 Gerrit-Change-Number: 86380 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 14:45:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86402?usp=email ) Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 14:29:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common: Add support for RTD3 on CNVi
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86403?usp=email ) Change subject: soc/intel/common: Add support for RTD3 on CNVi ...................................................................... Patch Set 7: -Code-Review This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 14:28:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, hualin wei. Subrata Banik has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/86404?usp=email ) Change subject: mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia32911488464af4e5070543e2ec630c339ab1925 Gerrit-Change-Number: 86404 Gerrit-PatchSet: 1 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 13:27:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86393?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel ...................................................................... soc/intel/pantherlake: Skip exposing CPUJTAG at kernel This patch avoids exposing CPUJTAG GPIO PADs as these are internal GPIO PINs used for SoC debugging purpose and shouldn't allow kernel level configuration. TEST=Able to build and boot google/fatat. Decompile ACPI table using iasl and ensure CPUJTAG entry not present. Change-Id: I4d920acb95275fbf72b83b822eddc41829511626 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/acpi/gpio.asl M src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h 2 files changed, 7 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/86393/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d920acb95275fbf72b83b822eddc41829511626 Gerrit-Change-Number: 86393 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/{intel,amd}/gpio: Correct SOC GPIO OP
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier. Hello Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86399?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/{intel,amd}/gpio: Correct SOC GPIO OP ...................................................................... soc/{intel,amd}/gpio: Correct SOC GPIO OP The current use of `acpigen_write_integer` called via `acpigen_soc_get_tx_gpio` will produce the below: ``` 0x6E = \_SB.PCI0.GTXS /* External reference */ Local0 ``` This does not work, as it includes the byte prefix. Change it to use `acpigen_emit_integer`, so that it produces: ``` Local0 = GTXS (0x6E) ``` This fixes an issue in Device Manager on Windows where devices report a power failure. Test=build and boot various starlabs boards, dump SSDT and verify it's correct. Change-Id: Id03d7ca0e328917fc8379adb967a2a122c7ff85f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/amd/common/block/acpi/gpio.c M src/soc/intel/common/block/acpi/gpio.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86399/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86399?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id03d7ca0e328917fc8379adb967a2a122c7ff85f Gerrit-Change-Number: 86399 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit February 2025