coreboot-gerrit February 2025

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Karthik Ramasubramanian (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 21:32:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86402?usp=email to look at the new patch set (#8). Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... drivers/wifi/generic: Add Methods to control CNVi enable GPIO Add two new methods, CNVS and CNVC, that can check and control the enable GPIO for a CNVi module. These will be used by the common code for RTD3. Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86402/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[M] Change in coreboot[main]: soc/intel/common: Add support for RTD3 on CNVi
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Sean Rhodes. Hello Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86403?usp=email to look at the new patch set (#9). Change subject: soc/intel/common: Add support for RTD3 on CNVi ...................................................................... soc/intel/common: Add support for RTD3 on CNVi Hook CNVC and CNVS Methods into the power resource for the CNVi which a provided via the `wifi/generic` driver to allow for RTD3. Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/wifi/generic/acpi.c M src/soc/intel/common/block/cnvi/cnvi.c 2 files changed, 85 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/86403/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: soc/amd/common/block/graphics: Use vbt_get()
by Jérémy Compostella (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, Patrick Rudolph, Ronak Kanabar. Jérémy Compostella has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86299?usp=email ) Change subject: soc/amd/common/block/graphics: Use vbt_get() ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/amd/common/block/graphics/graphics.c: https://review.coreboot.org/c/coreboot/+/86299/comment/86f38143_8c38dbad?us… : PS3, Line 151: if (!CONFIG(RUN_FSP_GOP)) > Done Just to reply with the code consistency. -- To view, visit https://review.coreboot.org/c/coreboot/+/86299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Gerrit-Change-Number: 86299 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 Feb 2025 21:19:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86402?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... drivers/wifi/generic: Add Methods to control CNVi enable GPIO Add two new methods, CNVS and CNVC, that can check and control the enable GPIO for a CNVi module. These will be used by the common code for RTD3. Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86402/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add GPIO driver
by Yu-Ping Wu (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Vince Liu. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85667?usp=email ) Change subject: soc/mediatek/mt8189: Add GPIO driver ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8189/gpio.c: https://review.coreboot.org/c/coreboot/+/85667/comment/8981f4dc_1ab63271?us… : PS2, Line 264: if (raw_id >= ARRAY_SIZE(gpio_driving_info)) Vince, could you upload another patch similar to CB:74063 to reduce the bootblock size? -- To view, visit https://review.coreboot.org/c/coreboot/+/85667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia87fe0975add95fcfad16d55586559c7f912a624 Gerrit-Change-Number: 85667 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 20:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Bora Guvendik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Bora Guvendik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 19:39:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Jérémy Compostella (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#7) to the change originally created by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... soc/intel/pantherlake: Enable multiple ACPI devices for GPIO In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file. The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community. Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal. Here are two notable changes in the fatcat board SSDT introduced by this commit. - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16) "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86290/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Jérémy Compostella (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#6) to the change originally created by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... soc/intel/pantherlake: Enable multiple ACPI devices for GPIO In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file. The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community. Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal. Here are two notable changes in the fatcat board SSDT introduced by this commit. - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16) "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86290/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Jérémy Compostella (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#5) to the change originally created by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... soc/intel/pantherlake: Enable multiple ACPI devices for GPIO In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file. The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community. Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal. Here are two notable changes in the fatcat board SSDT introduced by this commit. - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16) "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/86290/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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coreboot-gerrit February 2025