coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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2886 discussions

[S] Change in coreboot[main]: mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya remove Micron SPD data
by Uwe Poeche (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Werner Zeh. Uwe Poeche has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86423?usp=email ) Change subject: mb/siemens/fa_ehl/variants/fa_ehl/spd: Add Nanya remove Micron SPD data ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/mainboard/siemens/fa_ehl/variants/fa_ehl/spd/Nanya_NT6AP512T32BV-J1I.spd.hex: https://review.coreboot.org/c/coreboot/+/86423/comment/97d06b7c_fb7d326d?us… : PS2, Line 1: 23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 Just a formal thing from my point of view: exchange files would be more transparent via "git rm old" and "git add new". Also *.hex in file name does not suggest that it is an ascii format. But I think the format is fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/86423?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae Gerrit-Change-Number: 86423 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 15:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization
by John Su (Code Review) 19 Feb '25

19 Feb '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86514?usp=email ) Change subject: mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization ...................................................................... mb/trulo/var/uldrenite: Fix boot time caused by WWAN initialization Move WWAN power sequence to GPIO control to reduce boot time caused by WWAN initialization. BUG=b:383212261 BRANCH=firmware-trulo-15217.771.B TEST=Confirm the measured WWAN power sequence Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/variant.c M src/mainboard/google/brya/wwan_power.asl 4 files changed, 10 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86514/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index 3e11b48..e8355d3 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -232,9 +232,9 @@ /* F11 : NC */ PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : NC ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* F13 : NC ==> PLTRST_WWAN# */ - PAD_CFG_GPO(GPP_F13, 0, DEEP), + PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : NC */ PAD_NC(GPP_F14, NONE), /* F15 : NC */ @@ -303,7 +303,7 @@ /* H22 : NC */ PAD_NC(GPP_H22, NONE), /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* R0 : HDA_BCLK ==> HDA_BIT_CLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), @@ -435,7 +435,7 @@ /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 0, DEEP), + PAD_CFG_GPO(GPP_H23, 1, DEEP), }; /* Fill romstage gpio configuration */ @@ -445,6 +445,8 @@ PAD_CFG_GPO(GPP_E17, 1, DEEP), /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* F12 : NC ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h index 612ea2a..e752456 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h @@ -10,5 +10,6 @@ #define WWAN_PERST GPP_F13 #define T1_OFF_MS 20 #define T2_OFF_MS 10 +#define T0_OFF_MS 150 #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 41ab7b8..8a6f5a9 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -15,19 +15,6 @@ return "wifi_sar_0.hex"; } -static const struct pad_config rw350r_en_pad[] = { - /* H23 : LTE_PWR_OFF_EN */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), -}; -static const struct pad_config rw350r_rst_pad[] = { - /* F12 : WWAN_RST_L */ - PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), -}; -static const struct pad_config rw350r_perst_pad[] = { - /* F13 : PLTRST_WWAN# */ - PAD_CFG_GPO(GPP_F13, 1, DEEP), -}; - static const struct pad_config touchscreen_disable_pads[] = { /* A21 : TCHSCR_REPORT_EN */ PAD_NC(GPP_A21, NONE), @@ -68,18 +55,3 @@ } } -void variant_init(void) -{ - if (fw_config_probe(FW_CONFIG(DB_CELLULAR, CELLULAR_ABSENT))) - return; - /* - * RW350R power on seuqence: - * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms -> - * de-assert WWAN_PERST - */ - gpio_configure_pads(rw350r_en_pad, ARRAY_SIZE(rw350r_en_pad)); - mdelay(RW350R_RST_DELAY_MS); - gpio_configure_pads(rw350r_rst_pad, ARRAY_SIZE(rw350r_rst_pad)); - mdelay(RW350R_PERST_DELAY_MS); - gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad)); -} diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl index f19a5ef..4f9b788 100644 --- a/src/mainboard/google/brya/wwan_power.asl +++ b/src/mainboard/google/brya/wwan_power.asl @@ -11,4 +11,7 @@ \_SB.PCI0.CTXS(WWAN_RST); Sleep(T2_OFF_MS) \_SB.PCI0.CTXS(WWAN_FCPO); +#if CONFIG(BOARD_GOOGLE_ULDRENITE) + Sleep(T0_OFF_MS) +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/86514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd Gerrit-Change-Number: 86514 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: acpi: Fix incorrect TPM2 table generation for CRB_TPM
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Cliff Huang, Lance Zhao, Sean Rhodes, Tim Wawrzynczak. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86513?usp=email ) Change subject: acpi: Fix incorrect TPM2 table generation for CRB_TPM ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I153779aa1f3d84ffeb694543f9da1d09b120f98f Gerrit-Change-Number: 86513 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 14:32:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/usb/acpi: Account for GPIO polarity
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jérémy Compostella, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86400?usp=email ) Change subject: drivers/usb/acpi: Account for GPIO polarity ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib481d49d536b702fef149af882209501c61de6da Gerrit-Change-Number: 86400 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 14:08:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct HDMI HPD GPIO config
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86495?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct HDMI HPD GPIO config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I012acfa43ada5641b37f38892a1e3bfbc6e74843 Gerrit-Change-Number: 86495 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Wed, 19 Feb 2025 14:07:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for Librem mini v1/v2
by Jonathon Hall (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Matt DeVillier. Jonathon Hall has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/86470?usp=email ) Change subject: mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for Librem mini v1/v2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86470?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I047e6319b70f2747796869151bf361afe4c3e961 Gerrit-Change-Number: 86470 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 13:53:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD...
by Rui Zhou (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/86483?usp=email ) Change subject: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD more preparation time ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86483/comment/53dcd1e5_93cefede?us… : PS2, Line 2: zhourui > Please use your full name. Done https://review.coreboot.org/c/coreboot/+/86483/comment/85fa483a_c3f7457d?us… : PS2, Line 7: Adjust SSD power sequencing > Please be more specific. Done https://review.coreboot.org/c/coreboot/+/86483/comment/8e66bd60_76459c5d?us… : PS2, Line 9: Improve SSD reset time by enabling earlier sequencing. > How much reset time is saved? Done https://review.coreboot.org/c/coreboot/+/86483/comment/4d7f208a_da913513?us… : PS2, Line 15: zhou > Zhou Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86483?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Gerrit-Change-Number: 86483 Gerrit-PatchSet: 4 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Feb 2025 12:53:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD...
by Rui Zhou (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86483?usp=email to look at the new patch set (#4). Change subject: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD more preparation time ...................................................................... mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD more preparation time Improve SSD reset time by enabling earlier sequencing, save 230ms BUG=b:397098950 TEST=build and boot normal using NVMe Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86483/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86483?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Gerrit-Change-Number: 86483 Gerrit-PatchSet: 4 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Refactor SSD power sequencing
by Rui Zhou (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86483?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/rull: Refactor SSD power sequencing ...................................................................... mb/google/nissa/var/rull: Refactor SSD power sequencing Improve SSD reset time by enabling earlier sequencing. BUG=b:397098950 TEST=build and boot normal using NVMe Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86483/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86483?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567 Gerrit-Change-Number: 86483 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add FW_CONFIG probe for fivr
by Dtrain Hsu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86303?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add FW_CONFIG probe for fivr ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14233090f2445461cf422c1257f21556fd745b43 Gerrit-Change-Number: 86303 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Feb 2025 11:58:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025