coreboot-gerrit February 2025

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.2
by Yidi Lin (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, Yu-Ping Wu, agogo. Yidi Lin has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/86511?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.2 ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/blobs/+/86511/comment/d934ab8f_2e99a834?usp=e… : PS1, Line 9: Update coef for mcu-lvts reboot temp setting. Please update the commit message https://review.coreboot.org/c/blobs/+/86511/comment/0e0e96fe_8840b25c?usp=e… : PS1, Line 11: TEST=NA : BUG=b:317009620 BRANCH=rauru File soc/mediatek/mt8196/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/86511/comment/8d3bc56e_47e968d4?usp=e… : PS1, Line 12: coef coefficient https://review.coreboot.org/c/blobs/+/86511/comment/8c861feb_3e2ab6d1?usp=e… : PS1, Line 12: temp temperature https://review.coreboot.org/c/blobs/+/86511/comment/94560f8a_8b25e3bb?usp=e… : PS1, Line 12: mcu-lvts MCU-LVTS -- To view, visit https://review.coreboot.org/c/blobs/+/86511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I81e745a7290c31fe15240102df0a78dfaadf54e7 Gerrit-Change-Number: 86511 Gerrit-PatchSet: 1 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 16:47:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Generate SPD ID for supported parts
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86477?usp=email ) Change subject: mb/google/nissa/var/dirks: Generate SPD ID for supported parts ...................................................................... mb/google/nissa/var/dirks: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. K3KL9L90CM-MGCT (SAMSUNG) 2. H58G66BK8BX067 (HYNIX) BUG=b:388117663 TEST=Run part_id_gen tool and check the generated files. Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86477 Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/dirks/memory/Makefile.mk M src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: Ivy Jian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk index 2d0d1bb..67b6ac1 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk @@ -10,3 +10,5 @@ SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = H58G56BK8BX068 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 6(0b0110) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 7(0b0111) Parts = H58G66BK8BX067 diff --git a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt index c10bbb7..059f1e6 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt @@ -12,3 +12,5 @@ H9JCNNNCP3MLYR-N6E 0 (0000) K3KL8L80CM-MGCT 4 (0100) H58G56BK8BX068 5 (0101) +K3KL9L90CM-MGCT 6 (0110) +H58G66BK8BX067 7 (0111) diff --git a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt index 2c18a19..61be3e7 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt @@ -17,3 +17,5 @@ H9JCNNNCP3MLYR-N6E K3KL8L80CM-MGCT H58G56BK8BX068 +K3KL9L90CM-MGCT +H58G66BK8BX067 -- To view, visit https://review.coreboot.org/c/coreboot/+/86477?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0 Gerrit-Change-Number: 86477 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/byte: Set SYSTEM_TYPE_MINIPC
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86471?usp=email ) Change subject: mb/starlabs/byte: Set SYSTEM_TYPE_MINIPC ...................................................................... mb/starlabs/byte: Set SYSTEM_TYPE_MINIPC Ensures SMBIOS enclosure type set properly. Change-Id: I65ca75a57dbc4a9251316d48bf660dd631c716dd Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86471 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig index 77a4ea4..51fa7aa 100644 --- a/src/mainboard/starlabs/byte_adl/Kconfig +++ b/src/mainboard/starlabs/byte_adl/Kconfig @@ -10,6 +10,7 @@ select INTEL_LPSS_UART_FOR_CONSOLE select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SYSTEM_TYPE_MINIPC select VALIDATE_INTEL_DESCRIPTOR config BOARD_STARLABS_BYTE_ADL -- To view, visit https://review.coreboot.org/c/coreboot/+/86471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65ca75a57dbc4a9251316d48bf660dd631c716dd Gerrit-Change-Number: 86471 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for Librem mini v1/v2
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86470?usp=email ) Change subject: mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for Librem mini v1/v2 ...................................................................... mb/purism/librem_cnl: Set SYSTEM_TYPE_MINIPC for Librem mini v1/v2 Ensures SMBIOS enslosure type set properly. Change-Id: I047e6319b70f2747796869151bf361afe4c3e961 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86470 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jonathon Hall: Looks good to me, approved diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index ab6a67f..a718678 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -20,6 +20,7 @@ select HAVE_OPTION_TABLE select SOC_INTEL_WHISKEYLAKE select SUPERIO_ITE_IT8528E + select SYSTEM_TYPE_MINIPC config BOARD_PURISM_LIBREM_MINI_V2 select BOARD_PURISM_BASEBOARD_LIBREM_CNL @@ -27,6 +28,7 @@ select HAVE_OPTION_TABLE select SOC_INTEL_COMETLAKE_1 select SUPERIO_ITE_IT8528E + select SYSTEM_TYPE_MINIPC config BOARD_PURISM_LIBREM_14 select BOARD_PURISM_BASEBOARD_LIBREM_CNL -- To view, visit https://review.coreboot.org/c/coreboot/+/86470?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I047e6319b70f2747796869151bf361afe4c3e961 Gerrit-Change-Number: 86470 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya: Set SYSTEM_TYPE_MINIPC for brask baseboard boards
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86469?usp=email ) Change subject: mb/google/brya: Set SYSTEM_TYPE_MINIPC for brask baseboard boards ...................................................................... mb/google/brya: Set SYSTEM_TYPE_MINIPC for brask baseboard boards Brask devices are all Chromeboxes, so select SYSTEM_TYPE_MINIPC to ensure the SMBIOS enclosure type is set correctly. Change-Id: I133a26223ad204dfad67e136cf342d2fb2a7205e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86469 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9b0d59b..0f1c3c5 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -68,6 +68,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P + select SYSTEM_TYPE_MINIPC select TPM_GOOGLE_CR50 config BOARD_GOOGLE_BASEBOARD_HADES -- To view, visit https://review.coreboot.org/c/coreboot/+/86469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I133a26223ad204dfad67e136cf342d2fb2a7205e Gerrit-Change-Number: 86469 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/brya: Create moxie variant
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86061?usp=email ) Change subject: mb/google/brya: Create moxie variant ...................................................................... mb/google/brya: Create moxie variant Create the moxie variant of the kuldax project by copying the files to a new directory named for the variant. BUG=b:389391652 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MOXIE Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86061 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/moxie/Makefile.mk A src/mainboard/google/brya/variants/moxie/data.vbt A src/mainboard/google/brya/variants/moxie/fw_config.c A src/mainboard/google/brya/variants/moxie/gpio.c A src/mainboard/google/brya/variants/moxie/include/variant/ec.h A src/mainboard/google/brya/variants/moxie/include/variant/gpio.h A src/mainboard/google/brya/variants/moxie/overridetree.cb A src/mainboard/google/brya/variants/moxie/ramstage.c A src/mainboard/google/brya/variants/moxie/variant.c 11 files changed, 676 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, but someone else must approve Ren Kuo: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2e57055..9b0d59b 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -361,6 +361,14 @@ select BOARD_GOOGLE_BASEBOARD_BRASK select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_MOXIE + select BOARD_GOOGLE_BASEBOARD_BRASK + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_RAPTORLAKE + config BOARD_GOOGLE_NIVVIKS select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_32768 @@ -780,6 +788,7 @@ default 0x1 if BOARD_GOOGLE_MARASOV default 0x1 if BOARD_GOOGLE_MITHRAX default 0x1 if BOARD_GOOGLE_MOLI + default 0x1 if BOARD_GOOGLE_MOXIE default 0x0 if BOARD_GOOGLE_NEREID default 0x0 if BOARD_GOOGLE_NIVVIKS default 0x1 if BOARD_GOOGLE_NOVA @@ -862,6 +871,7 @@ default 13 if BOARD_GOOGLE_MARASOV default 13 if BOARD_GOOGLE_MITHRAX default 13 if BOARD_GOOGLE_MOLI + default 13 if BOARD_GOOGLE_MOXIE default 13 if BOARD_GOOGLE_NEREID default 13 if BOARD_GOOGLE_NIVVIKS default 13 if BOARD_GOOGLE_NOVA @@ -948,6 +958,7 @@ default "Marasov" if BOARD_GOOGLE_MARASOV default "Mithrax" if BOARD_GOOGLE_MITHRAX default "Moli" if BOARD_GOOGLE_MOLI + default "Moxie" if BOARD_GOOGLE_MOXIE default "Nereid" if BOARD_GOOGLE_NEREID default "Nivviks" if BOARD_GOOGLE_NIVVIKS default "Nokris" if BOARD_GOOGLE_NOKRIS @@ -1023,6 +1034,7 @@ default "marasov" if BOARD_GOOGLE_MARASOV default "mithrax" if BOARD_GOOGLE_MITHRAX default "moli" if BOARD_GOOGLE_MOLI + default "moxie" if BOARD_GOOGLE_MOXIE default "nereid" if BOARD_GOOGLE_NEREID default "nereid" if BOARD_GOOGLE_TEREID default "nivviks" if BOARD_GOOGLE_NIVVIKS diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 6007aa2..db99d32 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -98,6 +98,9 @@ config BOARD_GOOGLE_MOLI bool "-> Moli" +config BOARD_GOOGLE_MOXIE + bool "-> Moxie" + config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" diff --git a/src/mainboard/google/brya/variants/moxie/Makefile.mk b/src/mainboard/google/brya/variants/moxie/Makefile.mk new file mode 100644 index 0000000..e31aaa1 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/moxie/data.vbt b/src/mainboard/google/brya/variants/moxie/data.vbt new file mode 100644 index 0000000..7d14588 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/moxie/fw_config.c b/src/mainboard/google/brya/variants/moxie/fw_config.c new file mode 100644 index 0000000..42613af --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/fw_config.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } else { + printk(BIOS_INFO, "BT offload disabled\n"); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/moxie/gpio.c b/src/mainboard/google/brya/variants/moxie/gpio.c new file mode 100644 index 0000000..556e8b6 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/gpio.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* C3 : SML0CLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6), + /* C4 : SML0DATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + + /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/ec.h b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/moxie/overridetree.cb b/src/mainboard/google/brya/variants/moxie/overridetree.cb new file mode 100644 index 0000000..19a20a1 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/overridetree.cb @@ -0,0 +1,347 @@ +fw_config + field AUDIO 0 2 + option AUDIO_UNKNOWN 0 + option NAU88L25B_I2S 1 + end + field BJ_POWER 3 4 + option BJ_POWER_150W 0 + option BJ_POWER_230W 1 + option BJ_POWER_65W 2 + option BJ_POWER_135W 3 + end + field MB_USBC 6 7 + option TC_USB4 0 + option TC_USB3 1 + end + field USB_HUB 32 + option HUB_ABSENT 0 + option HUB_PRESENT 1 + end +end + +chip soc/intel/alderlake + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .enable_fast_vmode = 1, + }" + + register "sagv" = "SaGv_Enabled" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A0 + register "usb3_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A1 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 100, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "true" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 on + probe MB_USBC TC_USB4 + end + device ref tbt_pcie_rp1 on + probe MB_USBC TC_USB4 + end + device ref tbt_pcie_rp2 on + probe MB_USBC TC_USB4 + end + device ref tcss_dma0 on + probe MB_USBC TC_USB4 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on + probe AUDIO NAU88L25B_I2S + end + end + end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_leds" = "0x05af" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8125 and RTL8111K Ethernet NIC + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on + probe USB_HUB HUB_ABSENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port9 on + probe USB_HUB HUB_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on + probe USB_HUB HUB_ABSENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port1 on + probe USB_HUB HUB_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/moxie/ramstage.c b/src/mainboard/google/brya/variants/moxie/ramstage.c new file mode 100644 index 0000000..f4f80be --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/ramstage.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <fw_config.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_RPL_P_ID_5, 15, 138 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 138 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 138 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in moxie, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W + * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W + * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system + * power = 225W * 5A / 11.25A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 11250, + .bj_volts_mv = 20000 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brya/variants/moxie/variant.c b/src/mainboard/google/brya/variants/moxie/variant.c new file mode 100644 index 0000000..b7cba96 --- /dev/null +++ b/src/mainboard/google/brya/variants/moxie/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + NAU88L25B_I2S)); + + if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) { + config->tcss_aux_ori = 1; + config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3; + config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86061?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712 Gerrit-Change-Number: 86061 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Add Fn support and clean up Kconfig order
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86474?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/trulo/var/uldrenite: Add Fn support and clean up Kconfig order ...................................................................... mb/trulo/var/uldrenite: Add Fn support and clean up Kconfig order Support Fn key on uldrenite emits a scancode of 94 (0x5e) and order the Kconfig. BUG=b:394749952 TEST=fn + top row (F1~F12) keys work fine Change-Id: I92c1bd200f1849a460943bdb96ab122d464a0f40 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86474 Reviewed-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: John Su: Looks good to me, approved Subrata Banik: Looks good to me, approved Andy Ebrahiem: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 31948fbd..2e57055 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -643,12 +643,13 @@ select BOARD_GOOGLE_BASEBOARD_TRULO select BOARD_ROMSIZE_KB_32768 select CHROMEOS_WIFI_SAR if CHROMEOS - select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select DRIVERS_WWAN_FM350GL + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE - select DRIVERS_WWAN_FM350GL + select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select ENFORCE_MEM_CHANNEL_DISABLE + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA -- To view, visit https://review.coreboot.org/c/coreboot/+/86474?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92c1bd200f1849a460943bdb96ab122d464a0f40 Gerrit-Change-Number: 86474 Gerrit-PatchSet: 8 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: Kconfig: Rework SYSTEM_TYPE_XX to better map to SMBIOS
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86454?usp=email ) Change subject: Kconfig: Rework SYSTEM_TYPE_XX to better map to SMBIOS ...................................................................... Kconfig: Rework SYSTEM_TYPE_XX to better map to SMBIOS Add SYSTEM_TYPE_SERVER and SYSTEM_TYPE_ALL_INE_ONE; rename SYSTEM_TYPE_BOX to SYSTEM_TYPE_MINIPC. Map these entries to the analogous SMBIOS enclosure types. Follow-on patches will have mainboards select these new SYSTEM_TYPE entries as appropriate. Change-Id: I2a35101ccc60daf4863568216ef145c9c701140b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86454 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> --- M src/Kconfig M src/lib/smbios_defaults.c M src/mainboard/google/brya/Kconfig 3 files changed, 26 insertions(+), 12 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Andy Ebrahiem: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 1d71840..e4c8467 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -652,18 +652,11 @@ # load site-local kconfig to allow user specific defaults and overrides source "site-local/Kconfig" -config SYSTEM_TYPE_BOX - default n - bool - help - For devices like chromebox, mac-mini etc. These devices - without built-in display and operates on AC supply alone. - -config SYSTEM_TYPE_LAPTOP +config SYSTEM_TYPE_ALL_IN_ONE default n bool -config SYSTEM_TYPE_TABLET +config SYSTEM_TYPE_CONVERTIBLE default n bool @@ -671,7 +664,22 @@ default n bool -config SYSTEM_TYPE_CONVERTIBLE +config SYSTEM_TYPE_LAPTOP + default n + bool + +config SYSTEM_TYPE_MINIPC + default n + bool + help + For devices like chromebox, mac-mini etc. These devices + without built-in display and operates on AC supply alone. + +config SYSTEM_TYPE_SERVER + default n + bool + +config SYSTEM_TYPE_TABLET default n bool diff --git a/src/lib/smbios_defaults.c b/src/lib/smbios_defaults.c index 0ad6442..ba6b231 100644 --- a/src/lib/smbios_defaults.c +++ b/src/lib/smbios_defaults.c @@ -99,6 +99,12 @@ return SMBIOS_ENCLOSURE_CONVERTIBLE; else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) return SMBIOS_ENCLOSURE_DETACHABLE; + else if (CONFIG(SYSTEM_TYPE_SERVER)) + return SMBIOS_ENCLOSURE_MAIN_SERVER_CHASSIS; + else if (CONFIG(SYSTEM_TYPE_MINIPC)) + return SMBIOS_ENCLOSURE_MINI_PC; + else if (CONFIG(SYSTEM_TYPE_ALL_IN_ONE)) + return SMBIOS_ENCLOSURE_ALL_IN_ONE; else return SMBIOS_ENCLOSURE_DESKTOP; } diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index fc18f8f..31948fbd 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -97,7 +97,7 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_BOX + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_MINIPC select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE @@ -223,7 +223,7 @@ config BOARD_GOOGLE_DIRKS select BOARD_GOOGLE_BASEBOARD_NISSA select SOC_INTEL_TWINLAKE - select SYSTEM_TYPE_BOX + select SYSTEM_TYPE_MINIPC config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA -- To view, visit https://review.coreboot.org/c/coreboot/+/86454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a35101ccc60daf4863568216ef145c9c701140b Gerrit-Change-Number: 86454 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: mb/novacustom: add V5x0TU board (Meteor Lake)
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email ) ( 26 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/novacustom: add V5x0TU board (Meteor Lake) ...................................................................... mb/novacustom: add V5x0TU board (Meteor Lake) NovaCustom (Clevo) V5x0TU are two laptops with Intel Core Ultra (Meteor Lake) series processors. Two variants (V540TU and V560TU) are supported. Their EC firmware is different due to keyboard layout changes. On coreboot's side, the only difference are SMBIOS strings. Working: - DDR5 SODIMM in slot RAM2 - M.2 2280 PCIe slots - Thunderbolt, USB ports - Video outputs in OS and firmware via FSP GOP - I2C touchpad, webcam, SD Card reader - S0ix - Booting Ubuntu 24.04 with edk2 UefiPayload - Vboot, TPM measured boot VBT was extracted from Clevo Insyde firmware, version v1.07.2. Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82673 Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/novacustom/Kconfig A src/mainboard/novacustom/Kconfig.name A src/mainboard/novacustom/mtl-h/Kconfig A src/mainboard/novacustom/mtl-h/Kconfig.name A src/mainboard/novacustom/mtl-h/Makefile.mk A src/mainboard/novacustom/mtl-h/acpi/backlight.asl A src/mainboard/novacustom/mtl-h/acpi/mainboard.asl A src/mainboard/novacustom/mtl-h/board_info.txt A src/mainboard/novacustom/mtl-h/bootblock.c A src/mainboard/novacustom/mtl-h/cmos.default A src/mainboard/novacustom/mtl-h/cmos.layout A src/mainboard/novacustom/mtl-h/data.vbt A src/mainboard/novacustom/mtl-h/devicetree.cb A src/mainboard/novacustom/mtl-h/dsdt.asl A src/mainboard/novacustom/mtl-h/fadt.c A src/mainboard/novacustom/mtl-h/gpio.c A src/mainboard/novacustom/mtl-h/gpio_early.c A src/mainboard/novacustom/mtl-h/hda_verb.c A src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h A src/mainboard/novacustom/mtl-h/ramstage.c A src/mainboard/novacustom/mtl-h/romstage.c A src/mainboard/novacustom/mtl-h/vboot-rwab.fmd 22 files changed, 1,383 insertions(+), 0 deletions(-) Approvals: Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig new file mode 100644 index 0000000..e159480 --- /dev/null +++ b/src/mainboard/novacustom/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_NOVACUSTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/novacustom/*/Kconfig.name" + +endchoice + +source "src/mainboard/novacustom/*/Kconfig" + +config MAINBOARD_VENDOR + default "NovaCustom" + +endif # VENDOR_NOVACUSTOM diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name new file mode 100644 index 0000000..242b3bb --- /dev/null +++ b/src/mainboard/novacustom/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_NOVACUSTOM + bool "NovaCustom" diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig new file mode 100644 index 0000000..5d608b4 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -0,0 +1,105 @@ +config BOARD_NOVACUSTOM_MTLH_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_WIFI_GENERIC + select EC_DASHARO_EC + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_NOVACUSTOM_V5X0TU_BASE + bool + select BOARD_NOVACUSTOM_MTLH_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_NOVACUSTOM_V540TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +config BOARD_NOVACUSTOM_V560TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +if BOARD_NOVACUSTOM_MTLH_COMMON + +config MAINBOARD_DIR + default "novacustom/mtl-h" + +config MAINBOARD_PART_NUMBER + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "V540TU" if BOARD_NOVACUSTOM_V540TU + default "V560TU" if BOARD_NOVACUSTOM_V560TU + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware, for Windows Update + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 1024 + +config POST_DEVICE + default n + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_AB + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config TPM_PIRQ + default 0x61 # GPP_E01 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config EC_DASHARO_EC_FLASH_SIZE + default 0x40000 + +endif diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name new file mode 100644 index 0000000..ff079a0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -0,0 +1,7 @@ +comment "Meteor Lake H" + +config BOARD_NOVACUSTOM_V540TU + bool "V540TU (14\")" + +config BOARD_NOVACUSTOM_V560TU + bool "V560TU (16\")" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk new file mode 100644 index 0000000..9a35f5a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-y += gpio.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl new file mode 100644 index 0000000..01fa83e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl new file mode 100644 index 0000000..ec22903 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/dasharo/ec/acpi/ec.asl> + +Scope (\_SB) { + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt new file mode 100644 index 0000000..4b3db96 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: NovaCustom +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c new file mode 100644 index 0000000..8d06adc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default new file mode 100644 index 0000000..62715bc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout new file mode 100644 index 0000000..66b8665 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.layout @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/mtl-h/data.vbt b/src/mainboard/novacustom/mtl-h/data.vbt new file mode 100644 index 0000000..59c3c78 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/data.vbt Binary files differ diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb new file mode 100644 index 0000000..663d694 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -0,0 +1,316 @@ +chip soc/intel/meteorlake + # Common SoC configuration + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # SaGv configuration + register "sagv" = "SAGV_ENABLED" + + # Disable C1 and Package C-state auto-demotion + register "disable_c1_state_auto_demotion" = "1" + register "disable_package_c_state_demotion" = "1" + + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + + # Thermal + register "tcc_offset" = "10" # TCC of 100C + + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */ + [6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */ + }" + + register "tcss_ports" = "{ + [0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */ + [1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */ + }" + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0xa743 inherit + device ref system_agent on end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + [DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */ + }" + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB unused + register "device[1].name" = ""DD01"" + # TCP0 for Thunderbolt 4 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + # TCP1 unused + register "device[3].name" = ""DD03"" + # TCP2 for HDMI 2.1 + register "device[4].name" = ""DD04"" + # TCP3 unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end + device ref dtt on end + device ref pcie_rp10 on # M.2 2280 #2 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "srcclk_pin" = "8" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on # M.2 2280 #1 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "7" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref crashlog on end + device ref vpu on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref ioe_shared_sram on end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on # USB-PD EEPROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c3 on # Pantone ROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN" + end + device ref pcie_rp6 on # SD Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp8 on # M.2 2230 + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm # SLB 9672 TPM 2.0 + device pnp 0c31.0 on end + end + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_V" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_S" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 1 (TBT) + use usb2_port6 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 2 (Non-TBT) + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0xa763 + #register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl new file mode 100644 index 0000000..06e7263 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c new file mode 100644 index 0000000..f983717 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/novacustom/mtl-h/gpio.c b/src/mainboard/novacustom/mtl-h/gpio.c new file mode 100644 index 0000000..f52b044 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio.c @@ -0,0 +1,574 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group V ------- */ + + /* GPP_V00 - BATLOW# */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), + /* GPP_V01 - ACPRESENT */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), + /* GPP_V02 - SOC_WAKE# */ + PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), + /* GPP_V03 - PWRBTN# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + /* GPP_V04 - SLP_S3# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 - SLP_S4# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 - SLP_A# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07 - GPIO */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), + /* GPP_V08 - SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 - SLP_WLAN# */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 - SLP_S5# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 - LANPHYPC */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12 - SLP_LAN# */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13 - GPIO */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), + /* GPP_V14 - WAKE# */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15 - GPIO */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), + /* GPP_V16 - GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), + /* GPP_V17 - GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), + /* GPP_V18 - GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), + /* GPP_V19 - n/a */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), + /* GPP_V20 - n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), + /* GPP_V21 - n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), + /* GPP_V22 - GPIO */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + /* GPP_V23 - GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), + /* GPP_C02 - GPIO */ + PAD_CFG_GPO(GPP_C02, 0, DEEP), + /* GPP_C03 - SML0CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04 - SML0DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05 - GPIO */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_C06 - SML1CLK */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), + /* GPP_C07 - SML1DATA */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), + /* GPP_C08 - GPIO */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + /* GPP_C09 - GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), + /* GPP_C10 - GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* GPP_C11 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13 - GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* GPP_C14 - GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* GPP_C15 - GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* GPP_C16 - TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 - TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 - GPIO */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), + /* GPP_C19 - GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), + /* GPP_C20 - DDP2_CTRLCLK */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), + /* GPP_C21 - DDP2_CTRLDATA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* GPP_C23 - GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A00 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + /* GPP_A01 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + /* GPP_A02 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + /* GPP_A03 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + /* GPP_A04 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + /* GPP_A05 - ESPI_CLK */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + /* GPP_A06 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + /* GPP_A07 - GPIO */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), + /* GPP_A08 - GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), + /* GPP_A09 - GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), + /* GPP_A10 - GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* GPP_A11 - GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + /* GPP_A13 - GPIO */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 0, DEEP), + /* GPP_A15 - GPIO */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + /* GPP_A16 - RSVD */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + /* GPP_A18 - GPIO */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), + /* GPP_A19 - GPIO */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 - GPIO */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_A21 - PMCALERT# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NATIVE), + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NATIVE), + /* GPP_ESPI_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E00 - GPIO */ + PAD_CFG_GPO(GPP_E00, 0, DEEP), + /* GPP_E01 - GPIO */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), + /* GPP_E02 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), + /* GPP_E03 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), + /* GPP_E04 - GPIO */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + /* GPP_E05 - GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), + /* GPP_E06 - GPIO */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), + /* GPP_E07 - GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_E08 - GPIO */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + /* GPP_E09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI), + /* GPP_E10 - GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* GPP_E11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + /* GPP_E12 - GPIO */ + PAD_CFG_GPO(GPP_E12, 0, DEEP), + /* GPP_E13 - GPIO */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + /* GPP_E16 - VRALERT# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + /* GPP_E17 - GPIO */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + /* GPP_E18 - GPIO */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + /* GPP_E19 - GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + /* GPP_E20 - GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), + /* GPP_E21 - GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + /* GPP_THC0_GSPI_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H00 - GPIO */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), + /* GPP_H01 - GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), + /* GPP_H02 - GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), + /* GPP_H03 - GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), + /* GPP_H04 - GPIO */ + PAD_CFG_GPO(GPP_H04, 0, DEEP), + /* GPP_H05 - GPIO */ + PAD_CFG_GPO(GPP_H05, 0, DEEP), + /* GPP_H06 - I2C3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07 - I2C3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08 - GPIO */ + PAD_CFG_GPO(GPP_H08, 0, DEEP), + /* GPP_H09 - GPIO */ + PAD_CFG_GPO(GPP_H09, 0, DEEP), + /* GPP_H10 - GPIO */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + /* GPP_H11 - GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* GPP_H13 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 - GPIO */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + /* GPP_H15 - GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), + /* GPP_H16 - GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_H18 - GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), + /* GPP_H19 - I2C0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 - I2C0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 - I2C1_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 - I2C1_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + /* GPP_LPI3C1_CLK_LPBK - GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), + /* GPP_LPI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F00 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 - GPIO */ + PAD_CFG_GPO(GPP_F06, 0, DEEP), + /* GPP_F07 - GPIO */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + /* GPP_F08 - GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), + /* GPP_F09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* GPP_F11 - GPIO */ + PAD_CFG_GPO(GPP_F11, 0, DEEP), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + /* GPP_F14 - GPIO */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + /* GPP_F15 - GPIO */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* GPP_F16 - GPIO */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + /* GPP_F19 - GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + /* GPP_F23 - GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), + /* GPP_THC1_GSPI1_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), + /* GPP_GSPI0A_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + + /* GPP_VGPIO3_USB0 - GPP_VGPIO3_USB0 */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB1 - GPP_VGPIO3_USB1 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB2 - GPP_VGPIO3_USB2 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB3 - GPP_VGPIO3_USB3 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB4 - GPP_VGPIO3_USB4 */ + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB5 - GPP_VGPIO3_USB5 */ + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB6 - GPP_VGPIO3_USB6 */ + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB7 - GPP_VGPIO3_USB7 */ + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), + /* GPP_VGPIO3_TS0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_TS1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S00 - GPIO */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), + /* GPP_S01 - GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), + /* GPP_S02 - GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), + /* GPP_S03 - GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), + /* GPP_S04 - GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), + /* GPP_S05 - GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), + /* GPP_S06 - GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), + /* GPP_S07 - GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B00 - GPIO */ + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), + /* GPP_B01 - GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), + /* GPP_B02 - GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), + /* GPP_B03 - GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), + /* GPP_B04 - GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + /* GPP_B05 - GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), + /* GPP_B06 - GPIO */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B07 - GPIO */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), + /* GPP_B08 - GPIO */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + /* GPP_B09 - GPIO */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 - GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + /* GPP_B11 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + /* GPP_B19 - GPIO */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + /* GPP_B21 - GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* GPP_B22 - GPIO */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* GPP_ACI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D00 - GPIO */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), + /* GPP_D01 - GPIO */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02 - GPIO */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), + /* GPP_D03 - GPIO */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), + /* GPP_D04 - GPIO */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), + /* GPP_D05 - GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), + /* GPP_D06 - GPIO */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), + /* GPP_D07 - GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), + /* GPP_D08 - GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), + /* GPP_D09 - GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), + /* GPP_D10 - HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11 - HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* GPP_D12 - HDA_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* GPP_D13 - HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* GPP_D16 - GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + /* GPP_D17 - HDA_RST# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D18 - SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D19 - SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D20 - SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 - SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 - n/a */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + /* GPP_D23 - n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + /* GPP_BOOTHALT_B - n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), + + /* ------- GPIO Group VGPIO ------- */ + + /* VGPIO00 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), + /* VGPIO04 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), + /* VGPIO05 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), + /* VGPIO06 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO07 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO08 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO09 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO10 - VGPIO10 */ + PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), + /* VGPIO11 - VGPIO11 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), + /* VGPIO12 - VGPIO12 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), + /* VGPIO13 - VGPIO13 */ + PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), + /* VGPIO18 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO19 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO20 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO21 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO22 - VGPIO22 */ + PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), + /* VGPIO23 - VGPIO23 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), + /* VGPIO24 - VGPIO24 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), + /* VGPIO25 - VGPIO25 */ + PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), + /* VGPIO30 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), + /* VGPIO31 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), + /* VGPIO32 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), + /* VGPIO33 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), + /* VGPIO34 - VGPIO34 */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + /* VGPIO35 - VGPIO35 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + /* VGPIO36 - VGPIO36 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + /* VGPIO37 - VGPIO37 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), + /* VGPIO40 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), + /* VGPIO41 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), + /* VGPIO42 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), + /* VGPIO43 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), + /* VGPIO44 - VGPIO44 */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), + /* VGPIO45 - VGPIO45 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), + /* VGPIO46 - VGPIO46 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), + /* VGPIO47 - VGPIO47 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/gpio_early.c b/src/mainboard/novacustom/mtl-h/gpio_early.c new file mode 100644 index 0000000..c47883e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/hda_verb.c b/src/mainboard/novacustom/mtl-h/hda_verb.c new file mode 100644 index 0000000..cd7493e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/hda_verb.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h new file mode 100644 index 0000000..57924a6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c new file mode 100644 index 0000000..cd7031b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/dasharo/ec/acpi.h> +#include <mainboard/gpio.h> +#include <smbios.h> +#include <soc/ramstage.h> + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // Pinmux configuration + params->CnviRfResetPinMux = 0x194CE404; // GPP_F04 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F05 + + params->LidStatus = dasharo_ec_get_lid_state(); +} diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c new file mode 100644 index 0000000..8fdd9ec --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + }; + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd new file mode 100644 index 0000000..18a5027 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_GBE 8K + SI_ME + } + SI_BIOS { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 256 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Gerrit-Change-Number: 82673 Gerrit-PatchSet: 29 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/guren: Create empty variant for guren
by Matt DeVillier (Code Review) 19 Feb '25

19 Feb '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86492?usp=email ) Change subject: mb/google/nissa/var/guren: Create empty variant for guren ...................................................................... mb/google/nissa/var/guren: Create empty variant for guren Create the template files to a new directory named for the guren variant. BUG=b:397149037 BRANCH=firmware-nissa-15217.B TEST=None Change-Id: I23803aaceb122d2b9e3c2215914643593afa1246 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86492 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/guren/include/variant/ec.h A src/mainboard/google/brya/variants/guren/include/variant/gpio.h A src/mainboard/google/brya/variants/guren/memory/Makefile.mk A src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/guren/overridetree.cb 8 files changed, 49 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 213d499..fc18f8f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -295,6 +295,9 @@ select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select HAVE_WWAN_POWER_SEQUENCE +config BOARD_GOOGLE_GUREN + select BOARD_GOOGLE_BASEBOARD_NISSA + config BOARD_GOOGLE_HADES select BOARD_GOOGLE_BASEBOARD_HADES select DRIVERS_GENESYSLOGIC_GL9755 @@ -766,6 +769,7 @@ default 0x1 if BOARD_GOOGLE_GLADIOS default 0x0 if BOARD_GOOGLE_GLASSWAY default 0x0 if BOARD_GOOGLE_GOTHRAX + default 0x0 if BOARD_GOOGLE_GUREN default 0x3 if BOARD_GOOGLE_HADES default 0x0 if BOARD_GOOGLE_JOXER default 0x1 if BOARD_GOOGLE_KANO @@ -847,6 +851,7 @@ default 13 if BOARD_GOOGLE_GLADIOS default 13 if BOARD_GOOGLE_GLASSWAY default 13 if BOARD_GOOGLE_GOTHRAX + default 13 if BOARD_GOOGLE_GUREN default 20 if BOARD_GOOGLE_HADES # GPE0_DW0_20 (GPP_A20_IRQ) default 13 if BOARD_GOOGLE_JOXER default 13 if BOARD_GOOGLE_KANO @@ -932,6 +937,7 @@ default "Gladios" if BOARD_GOOGLE_GLADIOS default "Glassway" if BOARD_GOOGLE_GLASSWAY default "Gothrax" if BOARD_GOOGLE_GOTHRAX + default "Guren" if BOARD_GOOGLE_GUREN default "Hades" if BOARD_GOOGLE_HADES default "Joxer" if BOARD_GOOGLE_JOXER default "Kano" if BOARD_GOOGLE_KANO @@ -1006,6 +1012,7 @@ default "gladios" if BOARD_GOOGLE_GLADIOS default "glassway" if BOARD_GOOGLE_GLASSWAY default "gothrax" if BOARD_GOOGLE_GOTHRAX + default "guren" if BOARD_GOOGLE_GUREN default "hades" if BOARD_GOOGLE_HADES default "joxer" if BOARD_GOOGLE_JOXER default "kano" if BOARD_GOOGLE_KANO diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 50bfaef..6007aa2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -68,6 +68,9 @@ config BOARD_GOOGLE_GOTHRAX bool "-> Gothrax" +config BOARD_GOOGLE_GUREN + bool "-> Guren" + config BOARD_GOOGLE_HADES bool "-> Hades" diff --git a/src/mainboard/google/brya/variants/guren/include/variant/ec.h b/src/mainboard/google/brya/variants/guren/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/guren/include/variant/gpio.h b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/guren/overridetree.cb b/src/mainboard/google/brya/variants/guren/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/guren/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/86492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23803aaceb122d2b9e3c2215914643593afa1246 Gerrit-Change-Number: 86492 Gerrit-PatchSet: 4 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com>

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