coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Patrick Rudolph (Code Review) 04 Jan '25

04 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/f7a3d28b_22297bf6?us… : PS3, Line 7: Add fix for DPR silicon bug > Fix DPR silicon bug Will rephrase to workaround, the silicon cannot be fixed https://review.coreboot.org/c/coreboot/+/85829/comment/b7bbac37_1037f241?us… : PS3, Line 24: > Have you reported this bug to Intel, and are they going to release an errata? Unrelated. -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 08:09:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85850?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W pl1:15w(default) -> 22w 2.update the DPTF parameters were defined by the thermal team. BUG=b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/85850/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 3c04da5..9d91a45 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -152,7 +152,11 @@ .tdp_pl2_override = 25, .tdp_pl4 = 78, }" - + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -165,11 +169,11 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000), }" ## Critical Policy @@ -181,7 +185,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 6000, + .max_power = 13000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -197,8 +201,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 1500 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -222,11 +226,11 @@ .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(44, 61), + TEMP_PCT(42, 54), + TEMP_PCT(40, 45), + TEMP_PCT(38, 38), + TEMP_PCT(36, 25), } }, [1] = { @@ -277,7 +281,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -293,8 +297,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 2000 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -302,14 +306,14 @@ ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 100, 4000, 220, 1640, }, - [1] = { 90, 3700, 220, 1640, }, - [2] = { 80, 3500, 180, 1310, }, - [3] = { 70, 3300, 145, 1030, }, + [1] = { 90, 4100, 220, 1640, }, + [2] = { 80, 3800, 180, 1310, }, + [3] = { 70, 3500, 145, 1030, }, [4] = { 60, 3100, 115, 765, }, [5] = { 50, 2800, 90, 545, }, - [6] = { 40, 2500, 55, 365, }, - [7] = { 30, 2100, 30, 220, }, - [8] = { 20, 1500, 15, 120, }, + [6] = { 40, 2400, 55, 365, }, + [7] = { 30, 1900, 30, 220, }, + [8] = { 20, 1400, 15, 120, }, [9] = { 0, 0, 0, 50, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/85850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Gerrit-Change-Number: 85850 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85849?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 2.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85849/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Gerrit-Change-Number: 85849 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85849?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 2.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85849/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d2ad383..9ee5871 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -152,7 +152,11 @@ .tdp_pl2_override = 25, .tdp_pl4 = 78, }" - + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -165,11 +169,11 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000), }" ## Critical Policy @@ -181,7 +185,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 6000, + .max_power = 13000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -197,8 +201,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 1500 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -222,11 +226,11 @@ .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(44, 61), + TEMP_PCT(42, 54), + TEMP_PCT(40, 45), + TEMP_PCT(38, 38), + TEMP_PCT(36, 25), } }, [1] = { @@ -277,7 +281,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -293,8 +297,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 2000 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -302,14 +306,14 @@ ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 100, 4000, 220, 1640, }, - [1] = { 90, 3700, 220, 1640, }, - [2] = { 80, 3500, 180, 1310, }, - [3] = { 70, 3300, 145, 1030, }, + [1] = { 90, 4100, 220, 1640, }, + [2] = { 80, 3800, 180, 1310, }, + [3] = { 70, 3500, 145, 1030, }, [4] = { 60, 3100, 115, 765, }, [5] = { 50, 2800, 90, 545, }, - [6] = { 40, 2500, 55, 365, }, - [7] = { 30, 2100, 30, 220, }, - [8] = { 20, 1500, 15, 120, }, + [6] = { 40, 2400, 55, 365, }, + [7] = { 30, 1900, 30, 220, }, + [8] = { 20, 1400, 15, 120, }, [9] = { 0, 0, 0, 50, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/85849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idce6d61f3faf954c9ff591220962a07e6705c4ed Gerrit-Change-Number: 85849 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85848?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(default) -> 22W 1.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85848/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Gerrit-Change-Number: 85848 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85848?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(defualt) -> 22W 1.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85848/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Gerrit-Change-Number: 85848 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 03 Jan '25

03 Jan '25

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85848?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters 1.15W DUT: pl1 15W(defualt) -> 22W 1.The DPTF parameters were defined by the thermal team. BUG=b:387252007,b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 27 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85848/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d2ad383..9ee5871 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -152,7 +152,11 @@ .tdp_pl2_override = 25, .tdp_pl4 = 78, }" - + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 22, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -165,11 +169,11 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000), }" ## Critical Policy @@ -181,7 +185,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 6000, + .max_power = 13000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -197,8 +201,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 1500 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -222,11 +226,11 @@ .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(44, 61), + TEMP_PCT(42, 54), + TEMP_PCT(40, 45), + TEMP_PCT(38, 38), + TEMP_PCT(36, 25), } }, [1] = { @@ -277,7 +281,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 22000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -293,8 +297,8 @@ ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 3000 }, - [1] = { 24, 2000 }, + [0] = { 255, 4700 }, + [1] = { 40, 2500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" @@ -302,14 +306,14 @@ ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 100, 4000, 220, 1640, }, - [1] = { 90, 3700, 220, 1640, }, - [2] = { 80, 3500, 180, 1310, }, - [3] = { 70, 3300, 145, 1030, }, + [1] = { 90, 4100, 220, 1640, }, + [2] = { 80, 3800, 180, 1310, }, + [3] = { 70, 3500, 145, 1030, }, [4] = { 60, 3100, 115, 765, }, [5] = { 50, 2800, 90, 545, }, - [6] = { 40, 2500, 55, 365, }, - [7] = { 30, 2100, 30, 220, }, - [8] = { 20, 1500, 15, 120, }, + [6] = { 40, 2400, 55, 365, }, + [7] = { 30, 1900, 30, 220, }, + [8] = { 20, 1400, 15, 120, }, [9] = { 0, 0, 0, 50, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/85848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c8b96fe01a8b3f18edc6db9f27ff63d455bd7 Gerrit-Change-Number: 85848 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Anand Vaikar (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Ana Carolina Cabral, Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Anand Vaikar has posted comments on this change by Anand Vaikar. ( https://review.coreboot.org/c/coreboot/+/85749?usp=email ) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... Patch Set 9: (18 comments) File src/mainboard/amd/crater/Kconfig: https://review.coreboot.org/c/coreboot/+/85749/comment/1bfcb03f_1cfb5183?us… : PS8, Line 33: if BOARD_AMD_CRATER_RENOIR > this if is redundant, since this config option is already inside a "if BOARD_AMD_CRATER_RENOIR" bloc […] Done https://review.coreboot.org/c/coreboot/+/85749/comment/c4049fc0_307b7c3a?us… : PS8, Line 61: default "3rdparty/blobs/mainboard/amd/crater/EcSig_Crater.bin" > since this file isn't available in the public blobs repo, i'd say that we should have this in the . […] Done https://review.coreboot.org/c/coreboot/+/85749/comment/bd523f04_f2599b90?us… : PS8, Line 87: > there should only be one empty line Done https://review.coreboot.org/c/coreboot/+/85749/comment/e0cd50c4_bbd0a813?us… : PS8, Line 105: choice : prompt "I2C Speed Selection" : default SELECT_400KHz : help : Select Different speeds of I2C 400KHz / 1 MHz : : config SELECT_400KHz : bool "400KHz" : : config SELECT_1MHz : bool "1MHz" : : endchoice > not needed, since the i2c speed can and should be configured in the devicetree Done File src/mainboard/amd/crater/chromeos.c: https://review.coreboot.org/c/coreboot/+/85749/comment/a3acac6e_bcafcdb0?us… : PS8, Line 17: Birman > Crater Done File src/mainboard/amd/crater/chromeos_renoir.fmd: PS8: > not sure if the PSP_NVRAM and PSP_RPMC_NVRAM fmpa sections would easily fit into the fmap. […] sure, will take it up in subsequent patch. File src/mainboard/amd/crater/devicetree_renoir.cb: https://review.coreboot.org/c/coreboot/+/85749/comment/dbde155f_168ef3f2?us… : PS8, Line 3: > only one empty line Done https://review.coreboot.org/c/coreboot/+/85749/comment/5ea7090e_86b98ab0?us… : PS8, Line 43: register "gpp_clk_config[0]" = "GPP_CLK_ON" : register "gpp_clk_config[1]" = "GPP_CLK_ON" : register "gpp_clk_config[2]" = "GPP_CLK_ON" : register "gpp_clk_config[3]" = "GPP_CLK_ON" : register "gpp_clk_config[4]" = "GPP_CLK_ON" : register "gpp_clk_config[5]" = "GPP_CLK_ON" : register "gpp_clk_config[6]" = "GPP_CLK_ON" > haven't checked with the schematic, but some of those probably aren't correct. […] sure, will take it up in subsequent patch. File src/mainboard/amd/crater/early_gpio.c: https://review.coreboot.org/c/coreboot/+/85749/comment/d42798d9_b0250e48?us… : PS8, Line 13: > should be tab not spaces Done https://review.coreboot.org/c/coreboot/+/85749/comment/c857a4b2_0b4bb71d?us… : PS8, Line 70: }; > i'd add an empty line between the array and the function here Done File src/mainboard/amd/crater/ec.h: https://review.coreboot.org/c/coreboot/+/85749/comment/3a2be262_a9709062?us… : PS8, Line 7: void crater_boardrevision(void); > i'd add an empty line between the last function and the #endif Done File src/mainboard/amd/crater/ec.c: https://review.coreboot.org/c/coreboot/+/85749/comment/b0baf8f3_f5578e30?us… : PS8, Line 156: void crater_boardrevision(void) > hmm, i wonder if it would be cleaner if this file provides a function to get the board revision and […] sure will take it up in subsequent patches File src/mainboard/amd/crater/gpio.c: PS8: > this is probably missing some gpios will address in subsequent patch by reviewing the code. https://review.coreboot.org/c/coreboot/+/85749/comment/359b506a_e546457d?us… : PS8, Line 16: > tab Done File src/mainboard/amd/crater/port_descriptors_renoir.c: https://review.coreboot.org/c/coreboot/+/85749/comment/396596f5_45612cdd?us… : PS8, Line 96: ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); : BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3); > would be good to have a function in the mainboard's ec code for this will address this in subsequent patch https://review.coreboot.org/c/coreboot/+/85749/comment/473c85ee_ec940ef2?us… : PS8, Line 115: void __weak mainboard_fsp_mainboard_params_init(FSP_M_CONFIG *m_config) : { : : } > i don't see this function being needed or called, so it can likely be removed. […] Done File src/soc/amd/cezanne/chip.h: https://review.coreboot.org/c/coreboot/+/85749/comment/8c4da447_03e718ab?us… : PS8, Line 112: bool acp_i2s_use_external_48mhz_osc; > this and the corresponding change in the cezanne soc code should be done in a separate patch before […] Done File src/soc/amd/cezanne/include/soc/gpio.h: PS8: > this change should also be split out into a separate patch, so that the mainboard patch doesn't need […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 9 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Jan 2025 05:58:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
by Anand Vaikar (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Ana Carolina Cabral, Anand Vaikar, Bao Zheng, Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85749?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC ...................................................................... mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC 1) Initial commit for crater mainboard changes for RN/CZ SOC 2) Add the initial DXIO descriptors for crater 3) Add the DDI descriptors for crater 4) GPIO changes for crater mainboard TEST:Build crater mainboard changes with cezanne SOC Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- A src/mainboard/amd/crater/Kconfig A src/mainboard/amd/crater/Kconfig.name A src/mainboard/amd/crater/Makefile.mk A src/mainboard/amd/crater/board_info.txt A src/mainboard/amd/crater/board_renoir.fmd A src/mainboard/amd/crater/bootblock.c A src/mainboard/amd/crater/chromeos.c A src/mainboard/amd/crater/chromeos_renoir.fmd A src/mainboard/amd/crater/devicetree_renoir.cb A src/mainboard/amd/crater/dsdt.asl A src/mainboard/amd/crater/early_gpio.c A src/mainboard/amd/crater/ec.c A src/mainboard/amd/crater/ec.h A src/mainboard/amd/crater/gpio.c A src/mainboard/amd/crater/gpio.h A src/mainboard/amd/crater/mainboard.c A src/mainboard/amd/crater/port_descriptors_renoir.c 17 files changed, 909 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85749/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb276fc160326c666d5990e34de5327813d9403 Gerrit-Change-Number: 85749 Gerrit-PatchSet: 9 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Paul Menzel (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/a6a5ea61_9f5502e8?us… : PS3, Line 7: Add fix for DPR silicon bug Fix DPR silicon bug https://review.coreboot.org/c/coreboot/+/85829/comment/3f99f37a_8ac12fbc?us… : PS3, Line 20: snowridge Snow Ridge https://review.coreboot.org/c/coreboot/+/85829/comment/6cf3cff3_75148f86?us… : PS3, Line 24: Have you reported this bug to Intel, and are they going to release an errata? -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 04 Jan 2025 04:21:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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