coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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3269 discussions

[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Jayvik Desai (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Kapil Porwal, Paul Menzel, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Kapil Porwal, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85326?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Code-Review+1 by Boris Mittelberg, Code-Review+2 by Kapil Porwal, Verified+1 by build bot (Jenkins) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... ec/google/chromeec: Add debug timestamp for host EC commands Improve host EC command debugging with timestamps and duration for better analysis, this feature can be enabled by selecting the config EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG. BUG=none TEST=Brox/lotso device successfully built and booted. Debug messages confirmed in device logs only when the specific configuration is selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b, version: 0x0" Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec_lpc.c 2 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85326/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 19 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[XS] Change in coreboot[main]: mb/siemens/mc_ehl2: Limit eMMC speed mode to DDR50
by Werner Zeh (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/85881?usp=email ) Change subject: mb/siemens/mc_ehl2: Limit eMMC speed mode to DDR50 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I668bb5b0b3197497920b36bcf283c25d2a0c00ba Gerrit-Change-Number: 85881 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 08:40:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for...
by Werner Zeh (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Mario Scheithauer, Uwe Poeche. Werner Zeh has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/85864?usp=email ) Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Gerrit-Change-Number: 85864 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 08:39:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/acpi: Convert spaces to tabs
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85558?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/acpi: Convert spaces to tabs ...................................................................... soc/intel/xeon_sp/acpi: Convert spaces to tabs Cosmetic change only: Convert spaces to tabs. Change-Id: I0361b93bea44bb85477a3323198da612234397e8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85558 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/acpi/iiostack.asl 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl index c943dd5..c259746 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -70,10 +70,10 @@ #define IsCxlDomain Arg5 #define GrantedCxlFeatures Arg6 - Local7 = OscArg3 - CreateDWordField (OscArg3, Zero, RETE) - RETE = 0x0 - Local6 = ASL_UUID_UNHANDLED + Local7 = OscArg3 + CreateDWordField (OscArg3, Zero, RETE) + RETE = 0x0 + Local6 = ASL_UUID_UNHANDLED If ((OscArg1 != 0x01)) { @@ -116,7 +116,7 @@ CTRC &= GrantedCxlFeatures - /* TODO: further suppress CTRC bits per SUPC caps */ + /* TODO: further suppress CTRC bits per SUPC caps */ If ((CTRC != OTRC)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0361b93bea44bb85477a3323198da612234397e8 Gerrit-Change-Number: 85558 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: device: Fix debug print
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85807?usp=email ) Change subject: device: Fix debug print ...................................................................... device: Fix debug print Increase the char buffer size to fit all characters that are printed into it by the snprintf() call below. Change-Id: Ib153e1d02a08b2551dad5b51c4c88bf0bb606af3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85807 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/device/device_util.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/device/device_util.c b/src/device/device_util.c index 8d111b6..fc585a0 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -547,7 +547,7 @@ void report_resource_stored(struct device *dev, const struct resource *resource, const char *comment) { - char buf[10]; + char buf[16]; unsigned long long base, end; if (!(resource->flags & IORESOURCE_STORED)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib153e1d02a08b2551dad5b51c4c88bf0bb606af3 Gerrit-Change-Number: 85807 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: cpu/x86/64bit: Back up/restore CR3 on mode switch
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82164?usp=email ) Change subject: cpu/x86/64bit: Back up/restore CR3 on mode switch ...................................................................... cpu/x86/64bit: Back up/restore CR3 on mode switch Store CR3 on stack and restore it when returning from protected mode call, since the stage might have set up different page tables than the default ones linked into all stages. Tested: intel/archercity still boots to payload in x86_64. Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82164 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch.S 1 file changed, 10 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index e5be44a3..a4c58f2 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -26,6 +26,10 @@ /* Store stack pointer */ mov %rsp, %rbp + /* Backup cr3 to stack */ + mov %cr3, %rax + push %rax + /* New IDT to stack */ pushq $0 pushq $0 @@ -47,7 +51,7 @@ #include <cpu/x86/64bit/exit32.inc> /* Load zero IDT. x86_32 FSP doesn't like to find a x86_64 IDT */ - lidt -16(%ebp) + lidt -24(%ebp) /* Fetch function to call */ movl 12(%esp), %ebx @@ -56,8 +60,11 @@ call *%ebx movl %eax, %ebx - /* Preserves ebx */ - setup_longmode $PM4LE + /* + * Back to long mode by using cr3 previously stored on stack. + * Preserves ebx. + */ + setup_longmode -8(%ebp) /* Place return value in rax */ movl %ebx, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/82164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67 Gerrit-Change-Number: 82164 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Work around FSP bug
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85789?usp=email ) Change subject: cpu/x86/64bit/mode_switch: Work around FSP bug ...................................................................... cpu/x86/64bit/mode_switch: Work around FSP bug FSP, that is build against EDK2 2018 or newer, is able to back up and restore the bootloader IDT on entry/exit. Even though it sets up its own IDT, FSP checks the bootloader IDT size and deadloops without warning if it's too big. On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus x86_32 FSP might die on entry. Work around this issue by: * Back up and restore the IDT in protected_mode_call_wrapper * Load zero IDT in protected mode before jumping to function TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with exceptions in romstage enabled. Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85789 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch.S 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, but someone else must approve Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index 9555cef..e5be44a3 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -19,12 +19,22 @@ movl %gs, %eax push %rax + /* Backup IDT to stack */ + sub $16, %rsp + sidt (%rsp) + /* Store stack pointer */ mov %rsp, %rbp - /* Align stack and make space for arguments */ + /* New IDT to stack */ + pushq $0 + pushq $0 + + /* Align stack */ movabs $0xfffffffffffffff0, %rax andq %rax, %rsp + + /* Make room for arguments on stack */ sub $16, %rsp /* Arguments to stack */ @@ -36,6 +46,9 @@ /* Drop to protected mode */ #include <cpu/x86/64bit/exit32.inc> + /* Load zero IDT. x86_32 FSP doesn't like to find a x86_64 IDT */ + lidt -16(%ebp) + /* Fetch function to call */ movl 12(%esp), %ebx @@ -52,6 +65,10 @@ /* Restore stack pointer */ mov %rbp, %rsp + /* Restore IDT */ + lidt (%rsp) + add $16, %rsp + /* Restore registers */ pop %rbx movl %ebx, %gs -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Match VBT with SSFC
by Rui Zhou (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85875?usp=email ) Change subject: mb/google/nissa/var/rull: Match VBT with SSFC ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/rull/variant.c: https://review.coreboot.org/c/coreboot/+/85875/comment/bdf9e3c4_42850fbb?us… : PS2, Line 47: : static int get_ssfc(uint32_t *val) : { : static uint32_t known_value; : static enum { : SSFC_NOT_READ, : SSFC_AVAILABLE, : } ssfc_state = SSFC_NOT_READ; : : if (ssfc_state == SSFC_AVAILABLE) { : *val = known_value; : return 0; : } : : /* : * If SSFC field is not in the CBI then the value of SSFC will be 0 for : * further processing later since 0 of each bits group means default : * component in a variant. For more detail, please refer to cbi_ssfc.h. : */ : if (google_chromeec_cbi_get_ssfc(&known_value) != 0) { : printk(BIOS_DEBUG, "SSFC not set in CBI\n"); : return -1; : } : : ssfc_state = SSFC_AVAILABLE; : *val = known_value; : printk(BIOS_INFO, "SSFC 0x%x.\n", known_value); : return 0; : } > @kapilporwal@google.com […] do you mean ```src/ec/google/chromeec/ec.c```? i checked it and found that cmd is mainly used to obtain it. i personally think that the compatible code should be operated in private variant.c, at least it will not affect other projects and is convenient to operate. -- To view, visit https://review.coreboot.org/c/coreboot/+/85875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I413179af0a1346b7d21f17d728d6846c30707978 Gerrit-Change-Number: 85875 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 07:50:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,...,mc_ehl5}: Fix return in variant_mainboard_fin...
by Mario Scheithauer (Code Review) 07 Jan '25

07 Jan '25

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85891?usp=email ) Change subject: mb/siemens/{mc_ehl2,...,mc_ehl5}: Fix return in variant_mainboard_final() ...................................................................... mb/siemens/{mc_ehl2,...,mc_ehl5}: Fix return in variant_mainboard_final() If no resource is found for a device, do not return directly, otherwise the following code will no longer be executed. Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c 4 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/85891/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index ac3ab14..b384619 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -42,22 +42,21 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - disable_sdr_modes(res); + if (res) + disable_sdr_modes(res); } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c index d76ac03..c68ecda 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c @@ -33,13 +33,14 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c index 3ef72fd..64cb3f3 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -32,12 +32,13 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c index ac3ab14..b384619 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c @@ -42,22 +42,21 @@ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + if (res) { + disable_sdr_modes(res); - disable_sdr_modes(res); - - /* Use preset driver strength from preset value registers. */ - clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + /* Use preset driver strength from preset value + registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, + HOSTCTRL2_PRESET); + } } dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (dev) { struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - disable_sdr_modes(res); + if (res) + disable_sdr_modes(res); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Gerrit-Change-Number: 85891 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Configure Acoustic noise mitigation
by Subrata Banik (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kun Liu, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85863?usp=email ) Change subject: mb/google/nissa/var/rull: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54c8412410cca33ffb19a2b21d678b6263ead297 Gerrit-Change-Number: 85863 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 07:34:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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