coreboot-gerrit January 2025

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[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85859?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85859 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8186/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 13 files changed, 84 insertions(+), 12 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h similarity index 97% rename from src/soc/mediatek/common/dp/include/soc/dp_intf.h rename to src/soc/mediatek/common/dp/include/soc/dp_intf_common.h index 240a7e2..fceeb6d 100644 --- a/src/soc/mediatek/common/dp/include/soc/dp_intf.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_H -#define SOC_MEDIATEK_COMMON_DP_DP_INTF_H +#ifndef SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H #include <edid.h> #include <types.h> @@ -264,4 +264,4 @@ void dp_intf_config(const struct edid *edid); -#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h similarity index 89% rename from src/soc/mediatek/common/dp/include/soc/dptx.h rename to src/soc/mediatek/common/dp/include/soc/dptx_common.h index b473301..99b2ac2 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H #define DPTX_TBC_BUF_READSTARTADRTHRD 0x08 #define ENABLE_DPTX_EF_MODE 0x1 @@ -74,4 +74,4 @@ int mtk_edp_init(struct edid *edid); -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h similarity index 95% rename from src/soc/mediatek/common/dp/include/soc/dptx_hal.h rename to src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index d430b6a..778fe46 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H #define AUX_CMD_I2C_R_MOT0 0x1 #define AUX_CMD_I2C_R 0x5 @@ -100,4 +100,4 @@ void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value); void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable); -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */ diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h similarity index 99% rename from src/soc/mediatek/common/dp/include/soc/dptx_reg.h rename to src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h index a385eb8..a79c31f 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_reg.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_H -#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_H +#ifndef SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H +#define SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H #define TOP_OFFSET 0x2000 #define ENC0_OFFSET 0x3000 @@ -4737,4 +4737,4 @@ #define DPCD_69494 0x69494 #define DPCD_69518 0x69518 -#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_H */ +#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_REG_COMMON_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/dptx.h b/src/soc/mediatek/mt8186/include/soc/dptx.h new file mode 100644 index 0000000..221eae9e --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dptx.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_DPTX_H__ + +#include <soc/dptx_common.h> + +#endif /* __SOC_MEDIATEK_MT8186_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dp_intf.h b/src/soc/mediatek/mt8188/include/soc/dp_intf.h new file mode 100644 index 0000000..bb310c7 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dp_intf.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ + +#include <soc/dp_intf_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DP_INTF_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx.h b/src/soc/mediatek/mt8188/include/soc/dptx.h new file mode 100644 index 0000000..71a6ff6 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ + +#include <soc/dptx_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_hal.h b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h new file mode 100644 index 0000000..d6dcea6 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx_hal.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ + +#include <soc/dptx_hal_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8188/include/soc/dptx_reg.h b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h new file mode 100644 index 0000000..57cb853 --- /dev/null +++ b/src/soc/mediatek/mt8188/include/soc/dptx_reg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ +#define __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ + +#include <soc/dptx_reg_common.h> + +#endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_REG_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dp_intf.h b/src/soc/mediatek/mt8195/include/soc/dp_intf.h new file mode 100644 index 0000000..d6a000f --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dp_intf.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ + +#include <soc/dp_intf_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DP_INTF_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/mt8195/include/soc/dptx.h new file mode 100644 index 0000000..9af5b14 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ + +#include <soc/dptx_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h new file mode 100644 index 0000000..17dbf25 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ + +#include <soc/dptx_hal_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_HAL_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h new file mode 100644 index 0000000..9196005 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ +#define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ + +#include <soc/dptx_reg_common.h> + +#endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_REG_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,...,mc_ehl5}: Fix return in variant_mainboard_fin...
by Uwe Poeche (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Mario Scheithauer, Werner Zeh. Uwe Poeche has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/85891?usp=email ) Change subject: mb/siemens/{mc_ehl2,...,mc_ehl5}: Fix return in variant_mainboard_final() ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Gerrit-Change-Number: 85891 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 09:48:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for...
by Uwe Poeche (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Mario Scheithauer. Uwe Poeche has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/85864?usp=email ) Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl4}: Simplify SD code as well as for mc_ehl5 ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb Gerrit-Change-Number: 85864 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 09:37:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80100?usp=email ) Change subject: soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/80100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5ef78523c740f23807b3acf232f1c0e29feb4c6 Gerrit-Change-Number: 80100 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Guard function prototypes
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85595?usp=email ) Change subject: soc/intel/xeon_sp: Guard function prototypes ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85595/comment/68873f80_5c13e778?us… : PS1, Line 10: code. The defines will be used in the next commit. > Maybe to mention 'ASL' code to be more specific? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec Gerrit-Change-Number: 85595 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 09:03:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85561?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER ...................................................................... soc/intel/xeon_sp: Allow OS to control LTR and AER There's no reason to tell the OS to disable LTR. On UEFI and on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP. There's no SMM (RAS) code that is able to parse AER structures, thus let the OS always control AER. On coreboot's GNR AER is also always granted to the OS. TEST: Run code on ocp/tiogapass and observed dmesg: The OS now prints: acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR] Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85561/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Gerrit-Change-Number: 85561 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85559?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Use \_SB.POSC on all platforms ...................................................................... soc/intel/xeon_sp: Use \_SB.POSC on all platforms Reduce ACPI code size by using the existing \_SB.POSC instead of duplicating the method in every PCI/CXL host bridge. TEST: On ocp/tiogapass the OS still gets granted the PCIe capabilities as previously through _OSC. Reduces DSDT size by 1366 bytes. On ibm/sbp1 the OS still gets granted the PCIe capabilities as previously through _OSC. Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl 4 files changed, 20 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85559/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Gerrit-Change-Number: 85559 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Guard function prototypes
by Patrick Rudolph (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85595?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Guard function prototypes ...................................................................... soc/intel/xeon_sp: Guard function prototypes Guard function prototypes to allow the header to be used in ACPI ASL code. The defines will be used in the next commit. Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/acpi.h 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85595/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec Gerrit-Change-Number: 85595 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Kapil Porwal (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Paul Menzel, Subrata Banik. Kapil Porwal has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 19 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 08:53:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Jayvik Desai (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Paul Menzel, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 19: (1 comment) File src/ec/google/chromeec/Kconfig: https://review.coreboot.org/c/coreboot/+/85326/comment/3fc8e37c_eab9ffc4?us… : PS18, Line 101: depends on EC_GOOGLE_CHROMEEC_LPC > nit: this feature depends on presence of monotonic timer, please consider adding `depends on HAVE_MO […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 19 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 08:45:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Boris Mittelberg <bmbm(a)google.com>

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