coreboot-gerrit January 2025

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[M] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Nicholas Chin. Subrata Banik has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 7: (2 comments) File src/drivers/option/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85905/comment/c21f88d2_0e84812a?us… : PS6, Line 6: smm-$(CONFIG_USE_CBFS_FILE_OPTION_BACKEND) += cbfs_file_option.c > as we don't compile vboot library in smm mode, I'm getting compilation error due to undefined reference to `vb2_digest_size` and others > > ``` > HOSTCC cbfstool/bpdt_1_7.o > HOSTCC cbfstool/subpart_hdr_1.o > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0/smm/commonlib/bsd/cbfs_private.o: in function `cbfs_file_hash': > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/commonlib/bsd/cbfs_private.c:207: undefined reference to `vb2_digest_size' > HOSTCC cbfstool/subpart_hdr_2.o > HOSTCC cbfstool/subpart_entry_1.o > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0/smm/lib/cbfs.o: in function `vboot_hwcrypto_allowed': > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/security/vboot/misc.h:98: undefined reference to `vboot_get_context' > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/security/vboot/misc.h:98: undefined reference to `vb2api_hwcrypto_allowed' > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0/smm/lib/cbfs.o: in function `cbfs_file_hash_mismatch': > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/lib/cbfs.c:177: undefined reference to `vb2_hash_verify' > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/lib/cbfs.c:182: undefined reference to `vboot_get_context' > /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/lib/cbfs.c:182: undefined reference to `vboot_fail_and_reboot' > OBJCOPY bootblock.raw.bin > HOSTCC cbfstool/ifittool (link) > HOSTCC cbfstool/cse_fpt (link) > ``` > > I believe we don't want to link `FWLIB = ${BUILD}/vboot_fw.a` in smm? > > @jwerner@chromium.org thoughts ? should we drop `smm` stage compilation for cbfs_file_option.c ? File src/include/option.h: https://review.coreboot.org/c/coreboot/+/85905/comment/7289dac9_90c7645e?us… : PS7, Line 10: #if CONFIG(OPTION_BACKEND_NONE) ``` #if CONFIG(OPTION_BACKEND_NONE) || ENV_SMM ``` to avoid compiling newly added CBFS file into smm mode which resulted in vboot related compilation issue -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 13:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map I
by Patrick Rudolph (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Kevin Keijzer, Nicholas Chin, Paul Menzel. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85923?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map I ...................................................................... Patch Set 3: (3 comments) File src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85923/comment/6148ca07_0d506338?us… : PS3, Line 23: 0x0000000f It has 2 disabled, so superspeed_capable_ports should be 0xb File src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85923/comment/69239447_3f8c4781?us… : PS3, Line 22: 0x0000000f It has P1 disabled, so superspeed_capable_ports should be 0xd File src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85923/comment/cb2c9c1f_e864e36c?us… : PS3, Line 24: 0x0000000f It has P3 disabled, to probably superspeed_capable_ports should be 7 instead -- To view, visit https://review.coreboot.org/c/coreboot/+/85923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Gerrit-Change-Number: 85923 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 13:20:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS ...................................................................... soc/intel/ptl: Enable FSP debug log level control using CBFS This commit enables the FSP_DEBUG_LOG_LEVEL_USING_CBFS Kconfig option for Panther Lake ChromeOS devices. This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. Refer to the Kconfig help text for FSP_DEBUG_LOG_LEVEL_USING_CBFS for details on the valid log level values and how to set them using cbfstool. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 3 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86002/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 4f6f658..311520c 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -16,6 +16,7 @@ select DRIVERS_USB_ACPI select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 + select FSP_DEBUG_LOG_LEVEL_USING_CBFS if MAINBOARD_HAS_CHROMEOS select FSP_M_XIP select FSP_UGOP_EARLY_SIGN_OF_LIFE select FSP_USES_CB_DEBUG_EVENT_HANDLER diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index dfc47c6..8a5754e 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <cpu/intel/microcode.h> #include <fsp/api.h> +#include <fsp/debug.h> #include <fsp/fsp_debug_event.h> #include <fsp/fsp_gop_blt.h> #include <fsp/ppi/mp_service_ppi.h> @@ -685,7 +686,7 @@ /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) - && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + && CONFIG(FSP_ENABLE_SERIAL_DEBUG) && get_fsp_pcd_debug_log_level()) s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *) fsp_debug_event_handler); diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 033c4ea..464d925 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> +#include <fsp/debug.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -310,9 +311,14 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() : - FSP_LOG_LEVEL_DISABLE; - fsp_set_debug_level(m_cfg, log_level, log_level); + if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS) && is_enabled) { + fsp_set_debug_level(m_cfg, get_fsp_pcd_debug_log_level(), + get_fsp_mrc_debug_log_level()); + } else { + enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() : + FSP_LOG_LEVEL_DISABLE; + fsp_set_debug_level(m_cfg, log_level, log_level); + } if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) || (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0/: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 15 Jan '25

15 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0/: Add option to control debug log level using CBFS ...................................................................... drivers/intel/fsp2_0/: Add option to control debug log level using CBFS This commit introduces a new Kconfig option, FSP_DEBUG_LOG_LEVEL_USING_CBFS, which allows controlling the FSP debug log level using CBFS RAW binary files. If this option is enabled, the following files will be used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. The values in these files should correspond to the FSP_LOG_LEVEL_* enum values. See the Kconfig help text for more details. If this option is disabled, the log levels will be determined by calling into fsp_map_console_log_level API. This change allows for more flexibility in controlling the FSP debug log level, especially in cases of debugging silicon firmware issues with a debug AP FW binary. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO CBFS, both the silicon firmware and MRC behave as debug binaries. To verify the presence of both log-level RAW CBFS binaries in the CBFS RO slot, run: ``` sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_ ``` This should output: ``` option/fsp_mrc_debug_level 0x88e40 raw 8 none option/fsp_pcd_debug_level 0x2a7400 raw 8 none ``` Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 3 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86001/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c5c485b..8ab7d7b 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -522,4 +522,33 @@ Enable this option if you are using a debug build of the FSP (Firmware Support Package) in your project. +config FSP_DEBUG_LOG_LEVEL_USING_CBFS + bool + select HAVE_CBFS_FILE_OPTION_BACKEND + default n + help + Enable controlling the FSP debug log level using CBFS RAW binary files. + + If enabled, the following files will be used to determine the log levels: + + - `fsp_pcd_debug_level`: For the overall FSP debug log level. + - `fsp_mrc_debug_level`: For the MRC (Memory Reference Code) debug log level. + + Here is the example of adding RAW binary file into the RO-CBFS to specify the + FSP log-level: + - cbfstool <AP FW image> add-int -i <log-level> -n fsp_pcd_debug_level + - cbfstool <AP FW image> add-int -i <log-level> -n fsp_mrc_debug_level + + If disabled, the log levels will be determined by calling into + `fsp_map_console_log_level` API. + + As per FSP documentation of valid log-level values for these CBFS files: + 0: Serial log disable + 1: Critical errors, need action etc., FSP_LOG_LEVEL_ERR aka value 1 + 2. #1 including warnings, FSP_LOG_LEVEL_ERR_WARN aka value 2 + 3. #2 including additional informational messages, FSP_LOG_LEVEL_ERR_WARN_INFO + aka value 3 + 4. #3 including event logs, FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT aka value 4 + 5. Use FSP_LOG_LEVEL_VERBOSE aka 5 for all types of debug messages. + endif diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 9dc964d..339deeb 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -6,6 +6,7 @@ #include <cpu/x86/mtrr.h> #include <fsp/debug.h> #include <fsp/util.h> +#include <option.h> enum fsp_call_phase { BEFORE_FSP_CALL, @@ -178,3 +179,22 @@ display_mtrrs(); } + +#define FSP_PCD_DEBUG_FILENAME "fsp_pcd_debug_level" +#define FSP_MRC_DEBUG_FILENAME "fsp_mrc_debug_level" + +enum fsp_log_level get_fsp_pcd_debug_log_level(void) +{ + if (!CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS)) + return FSP_LOG_LEVEL_DISABLE; + + return (enum fsp_log_level)get_uint_option(FSP_PCD_DEBUG_FILENAME, FSP_LOG_LEVEL_DISABLE); +} + +enum fsp_log_level get_fsp_mrc_debug_log_level(void) +{ + if (!CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS)) + return FSP_LOG_LEVEL_DISABLE; + + return (enum fsp_log_level)get_uint_option(FSP_MRC_DEBUG_FILENAME, FSP_LOG_LEVEL_DISABLE); +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index e7f9f25..c1360a9 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -63,4 +63,29 @@ /* Callback to verify that current GPIO configuration matches the saved snapshot */ size_t gpio_verify_snapshot(void); +/* + * Retrieve `fsp_pcd_debug_level` file from CBFS to identify the log-level + * used for outputting FSP debug messages. + * If `fsp_pcd_debug_level` not present then, use the log-level as zero aka + * no serial log. Otherwise, use below log levels + * + * 1. Critical errors, need action etc., FSP_LOG_LEVEL_ERR aka value 1 + * 2. #1 including warnings, FSP_LOG_LEVEL_ERR_WARN aka value 2 + * 3. #2 including additional informational messages, FSP_LOG_LEVEL_ERR_WARN_INFO aka value 3 + */ +enum fsp_log_level get_fsp_pcd_debug_log_level(void); +/* +* Retrieve `fsp_mrc_debug_level` file from CBFS to identify the log-level +* used for outputting FSP debug messages. +* If `fsp_mrc_debug_level` not present then, use the log-level as zero aka +* no serial log. Otherwise, use below log levels +* +* 1. Critical errors, need action etc., FSP_LOG_LEVEL_ERR aka value 1 +* 2. #1 including warnings, FSP_LOG_LEVEL_ERR_WARN aka value 2 +* 3. #2 including additional informational messages, FSP_LOG_LEVEL_ERR_WARN_INFO aka value 3 +* 4. #3 including event logs, FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT aka value 4 +* 5. Use FSP_LOG_LEVEL_VERBOSE aka 5 for all types of debug messages. +*/ +enum fsp_log_level get_fsp_mrc_debug_log_level(void); + #endif /* _FSP2_0_DEBUG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure firmware display for eDP panel
by Yidi Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Nancy Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85952?usp=email ) Change subject: mb/google/rauru: Configure firmware display for eDP panel ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85952/comment/984ac950_100b8077?us… : PS4, Line 103: mt6373_init_pmif_arb(); : mt6373_enable_vcn33_3(true); : mt6373_set_vcn33_3_voltage(3300000); Move those call to a separate function. ``` static void enable_display_power_rail(void) { mt6373_init_pmif_arb(); mt6373_enable_vcn33_3(true); mt6373_set_vcn33_3_voltage(3300000); } ... if (display_init_required()) { enable_display_power_rail(); mtk_display_init(); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036 Gerrit-Change-Number: 85952 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 13:13:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Nancy Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... Patch Set 3: (3 comments) File src/soc/mediatek/common/display.c: https://review.coreboot.org/c/coreboot/+/85950/comment/555eebcd_5813c593?us… : PS2, Line 46: __weak int mtk_edp_enable(void) > Why do the past platforms (mt8195/mt8188) not follow this flow ? mt8195/mt8188 should have the same issue. The more logs you print, the greater the chance you will see the issue. File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/452a32f7_5b6e377e?us… : PS3, Line 267: setbits32(&exdma2_reg->rdma_burst_ctl, BIT(28)); : clrbits32(&exdma2_reg->rdma_burst_ctl, BIT(30)); : setbits32(&exdma2_reg->rdma_burst_ctl, BIT(31)); : setbits32(&exdma2_reg->dummy, BIT(2)); : setbits32(&exdma2_reg->dummy, BIT(3)); : setbits32(&exdma2_reg->datapath_con, BIT(0)); : setbits32(&exdma2_reg->datapath_con, BIT(24)); : setbits32(&exdma2_reg->datapath_con, BIT(25)); : clrbits32(&exdma2_reg->ovl_mout, BIT(0)); : setbits32(&exdma2_reg->ovl_mout, BIT(1)); > can we use `clrsetbits32` for those settings ? ok, I will fix it. File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85950/comment/ab90fa25_8abb13d0?us… : PS3, Line 198: MMSYS_MUTEX_BASE = IO_PHYS + 0x22020000, > move to line 190 OK, I will fix it -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 13:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Update 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Rui Zhou has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/86000?usp=email ) Change subject: mb/google/nissa/var/telith: Update 6W and 15W DPTF parameters ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06 Gerrit-Change-Number: 86000 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 13:02:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Update 6W and 15W DPTF parameters
by Kun Liu (Code Review) 15 Jan '25

15 Jan '25

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86000?usp=email ) Change subject: mb/google/nissa/var/telith: Update 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/telith: Update 6W and 15W DPTF parameters The DPTF parameters were defined by the thermal team. Based on thermal table in 377955793#comment20 BUG=b:377955793 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/telith/overridetree.cb 1 file changed, 11 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86000/1 diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index 8784e2f..231d83e 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -165,7 +165,7 @@ # Power limit config register "power_limits_config[ADL_N_041_6W_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 20, + .tdp_pl2_override = 25, .tdp_pl4 = 78, }" register "power_limits_config[ADL_N_081_15W_CORE]" = "{ @@ -208,8 +208,8 @@ .granularity = 200 }, .pl2 = { - .min_power = 20000, - .max_power = 20000, + .min_power = 25000, + .max_power = 25000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000 @@ -242,41 +242,29 @@ [0] = { .target = DPTF_TEMP_SENSOR_0, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(54, 64), - TEMP_PCT(52, 52), - TEMP_PCT(50, 44), - TEMP_PCT(48, 38), - TEMP_PCT(45, 34), + TEMP_PCT(73, 100), + TEMP_PCT(43, 20), } }, [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(75, 90), - TEMP_PCT(70, 80), - TEMP_PCT(65, 70), - TEMP_PCT(60, 60), - TEMP_PCT(55, 50), - TEMP_PCT(50, 40), + TEMP_PCT(60, 100), + TEMP_PCT(38, 20), } }, [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(90, 90), - TEMP_PCT(85, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 50), + TEMP_PCT(58, 100), + TEMP_PCT(36, 20), } }, [3] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(80, 90), - TEMP_PCT(75, 80), - TEMP_PCT(70, 70), - TEMP_PCT(65, 50), + TEMP_PCT(72, 100), + TEMP_PCT(41, 20), } } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/86000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06 Gerrit-Change-Number: 86000 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Yidi Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Nancy Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... Patch Set 3: (3 comments) File src/soc/mediatek/common/display.c: https://review.coreboot.org/c/coreboot/+/85950/comment/7a8cdb45_80adb8f1?us… : PS2, Line 46: __weak int mtk_edp_enable(void) > This can't merged into mtk_edp_init. […] Why do the past platforms (mt8195/mt8188) not follow this flow ? File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/548af839_ac551f50?us… : PS3, Line 267: setbits32(&exdma2_reg->rdma_burst_ctl, BIT(28)); : clrbits32(&exdma2_reg->rdma_burst_ctl, BIT(30)); : setbits32(&exdma2_reg->rdma_burst_ctl, BIT(31)); : setbits32(&exdma2_reg->dummy, BIT(2)); : setbits32(&exdma2_reg->dummy, BIT(3)); : setbits32(&exdma2_reg->datapath_con, BIT(0)); : setbits32(&exdma2_reg->datapath_con, BIT(24)); : setbits32(&exdma2_reg->datapath_con, BIT(25)); : clrbits32(&exdma2_reg->ovl_mout, BIT(0)); : setbits32(&exdma2_reg->ovl_mout, BIT(1)); can we use `clrsetbits32` for those settings ? File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85950/comment/657050b9_e6f0f9a7?us… : PS3, Line 198: MMSYS_MUTEX_BASE = IO_PHYS + 0x22020000, move to line 190 -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 12:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: Upgrade GCC to 15-20250112 Snapshot
by Elyes Haouas (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Christian Walter, Elyes Haouas, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Upgrade GCC to 15-20250112 Snapshot ...................................................................... Upgrade GCC to 15-20250112 Snapshot Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-15-20250112_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20250112_gnat.patch R util/crossgcc/patches/gcc-15-20250112_libcpp.patch R util/crossgcc/patches/gcc-15-20250112_libgcc.patch R util/crossgcc/patches/gcc-15-20250112_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20250112_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20250112.tar.xz.cksum 9 files changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Carlos López <carlos.lopezr4096(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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