coreboot-gerrit September 2024

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[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84178?usp=email ) Change subject: soc/intel/common/block: Include register offsets for POWER_CTL ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84178/comment/a348e7f1_7b0e1b52?us… : PS2, Line 7: src/soc/intel/cmn/block/inc: > soc/intel/common/block: Include register offsets for `POWER_CTL` Acknowledged https://review.coreboot.org/c/coreboot/+/84178/comment/d3d121d6_87575245?us… : PS2, Line 10: 1fc > 0x1fc Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Gerrit-Change-Number: 84178 Gerrit-PatchSet: 2 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 04:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/block: Include register offsets for POWER_CTL
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Saurabh Mishra. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84178?usp=email to look at the new patch set (#3). Change subject: soc/intel/common/block: Include register offsets for POWER_CTL ...................................................................... soc/intel/common/block: Include register offsets for POWER_CTL Details: - Add (POWER_CTL) – Offset 0x1fc required bits. Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/msr.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84178/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Gerrit-Change-Number: 84178 Gerrit-PatchSet: 3 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>

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[XS] Change in coreboot[main]: src/include/cpu/x86: Add Misc Enable and Thermal Interrupt Register M...
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Subrata Banik. Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84174?usp=email to look at the new patch set (#9). Change subject: src/include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro ...................................................................... src/include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro Details: - Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/cpu/x86/msr.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 9 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: src/include/cpu/x86: Add Extended Feature Enable Register Macro
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84174/comment/37d115c6_8f5e5843?us… : PS8, Line 7: Extended Feature Enable Register Macro > please add the correct description Updated the description. https://review.coreboot.org/c/coreboot/+/84174/comment/6c29463f_681b2425?us… : PS8, Line 10: 1b2 > isn't this is hex, hence, 0x1B2 Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 8 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 04:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 77: (3 comments) File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/fc04bd1b_dd235956?us… : PS50, Line 138: map > OK, sure, i have implemeted the flag "initialized", and added the above suggested snippet. Done File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/5ad48482_8c8cd12f?us… : PS55, Line 238: PCI_DEVFN_IGD > Sure, this is correct, as chipset.cb has default GFX enabled. […] Done File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/45201dd6_e503cb4f?us… : PS71, Line 126: if (!initialized) { > Please check and share your input. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 77 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 04:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Generate RAM IDs
by Tyler Wang (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Bob Moragues, David Wu, Karthik Ramasubramanian, Ren Kuo. Tyler Wang has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84193?usp=email ) Change subject: mb/google/brox/jubilant: Generate RAM IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Gerrit-Change-Number: 84193 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 04:23:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Yu-Ping Wu (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... Patch Set 16: (7 comments) File src/soc/mediatek/mt8196/gpio_eint.c: https://review.coreboot.org/c/coreboot/+/84026/comment/998e0a85_df3b5710?us… : PS16, Line 11: #define EINT_DUMMY 0 Use enum. https://review.coreboot.org/c/coreboot/+/84026/comment/fb678592_11aa7d84?us… : PS16, Line 11: DUMMY INVALID https://review.coreboot.org/c/coreboot/+/84026/comment/e55d85ef_98d8abfc?us… : PS16, Line 267: Add `uint8_t index = eint_data[idx].index`. https://review.coreboot.org/c/coreboot/+/84026/comment/aca7e903_4201cc8a?us… : PS16, Line 275: void * uintptr_t https://review.coreboot.org/c/coreboot/+/84026/comment/4081e435_667d2e75?us… : PS16, Line 282: (void *) Remove https://review.coreboot.org/c/coreboot/+/84026/comment/eebf7421_1146f282?us… : PS16, Line 297: addr = NULL; Print an error and return NULL. Is this considered an error? https://review.coreboot.org/c/coreboot/+/84026/comment/48410ab8_a93480bb?us… : PS16, Line 301: addr `(void *)addr` -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 16 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 03:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Generate RAM IDs
by Kenneth Chan (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Bob Moragues, David Wu, Karthik Ramasubramanian, Ren Kuo, Tyler Wang. Kenneth Chan has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84193?usp=email ) Change subject: mb/google/brox/jubilant: Generate RAM IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Gerrit-Change-Number: 84193 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 03:24:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Generate RAM IDs
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Bob Moragues, David Wu, Karthik Ramasubramanian, Kenneth Chan, Ren Kuo, Tyler Wang. Subrata Banik has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84193?usp=email ) Change subject: mb/google/brox/jubilant: Generate RAM IDs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Gerrit-Change-Number: 84193 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 03:24:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox/jubilant: Generate RAM IDs
by Ren Kuo (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Bob Moragues, David Wu, Karthik Ramasubramanian, Kenneth Chan, Tyler Wang. Hello David Wu, Karthik Ramasubramanian, Kenneth Chan, Tyler Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84193?usp=email to look at the new patch set (#2). Change subject: mb/google/brox/jubilant: Generate RAM IDs ...................................................................... mb/google/brox/jubilant: Generate RAM IDs Generate RAM IDs of lp5 memory: 1)Hyinx 4GB*4 H58G56BK8BX068 2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk M src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt M src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt 3 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/84193/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a Gerrit-Change-Number: 84193 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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coreboot-gerrit September 2024