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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/var/bujia: Add PSYS setting
......................................................................
mb/google/brask/var/bujia: Add PSYS setting
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/Makefile.mk
A src/mainboard/google/brya/variants/bujia/ramstage.c
2 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/13
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/var/bujia: Add PSYS setting
......................................................................
mb/google/brask/var/bujia: Add PSYS setting
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/Makefile.mk
A src/mainboard/google/brya/variants/bujia/ramstage.c
2 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/12
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Change subject: mb/google/brask/var/bujia: Add PSYS setting
......................................................................
mb/google/brask/var/bujia: Add PSYS setting
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/Makefile.mk
A src/mainboard/google/brya/variants/bujia/ramstage.c
2 files changed, 88 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/11
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/var/bujia: Add PSYS setting
......................................................................
mb/google/brask/var/bujia: Add PSYS setting
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/Makefile.mk
A src/mainboard/google/brya/variants/bujia/ramstage.c
2 files changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/83593/10
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Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao.
Hello Zheng Bao,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84195?usp=email
to review the following change.
Change subject: cezanne: Add recovery AB support option
......................................................................
cezanne: Add recovery AB support option
The Cezanne platform supports both A/B recovery and Non A/B recovery.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.mk
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84195/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index abeaece..e50073a 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -408,6 +408,12 @@
help
Add psp_verstage signature token to the build & PSP Directory Table
+config PSP_RECOVERY_AB
+ bool "Recovery A/B"
+ default n
+ help
+ Recovery A/B
+
endmenu
config VBOOT
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk
index adbf3a6..2747622 100644
--- a/src/soc/amd/cezanne/Makefile.mk
+++ b/src/soc/amd/cezanne/Makefile.mk
@@ -182,6 +182,8 @@
OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
+OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab)
+
AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
$(OPT_PSP_NVRAM_BASE) \
$(OPT_PSP_NVRAM_SIZE) \
@@ -204,6 +206,7 @@
$(OPT_EFS_SPI_READ_MODE) \
$(OPT_EFS_SPI_SPEED) \
$(OPT_EFS_SPI_MICRON_FLAG) \
+ $(OPT_RECOVERY_AB) \
--config $(CONFIG_AMDFW_CONFIG_FILE) \
--flashsize $(CONFIG_ROM_SIZE)
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Hello Zheng Bao,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84194?usp=email
to review the following change.
Change subject: amdfwtool: Set L2 table size as 0x400
......................................................................
amdfwtool: Set L2 table size as 0x400
The Max size of L2 table is 0x400. If we set it to other value, the
the A/B recovery image can not boot on Cezann/Majolica platform.
The affected boards are birman, Chausie, Skyrim, mayan. Other boards
are binary identical. Tested on Skyrim and image can boot.
Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/84194/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 1fe9923..1d94e06 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -870,7 +870,7 @@
BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
pspdir->entries[count].address_mode =
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
- pspdir->entries[count].size = _MAX(TABLE_ALIGNMENT,
+ pspdir->entries[count].size = _MAX(TABLE_L2_SIZE_MAX,
pspdir2->header.num_entries *
sizeof(psp_directory_entry) +
sizeof(psp_directory_header));
@@ -1216,11 +1216,11 @@
if (cb_config->recovery_ab) {
add_psp_firmware_entry(ctx, ctx->pspdir2, ctx->biosdir2,
- AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
+ AMD_FW_BIOS_TABLE, TABLE_L2_SIZE_MAX);
if (ctx->pspdir2_b != NULL)
add_psp_firmware_entry(ctx, ctx->pspdir2_b,
ctx->biosdir2_b, AMD_FW_BIOS_TABLE,
- TABLE_ALIGNMENT);
+ TABLE_L2_SIZE_MAX);
} else if (ctx->biosdir2) {
current_table_save = ctx->current_table;
ctx->current_table = BUFF_TO_RUN_MODE(*ctx, ctx->biosdir, AMD_ADDR_REL_BIOS);
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index b2fd2c0..b1d17d9 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -11,6 +11,7 @@
#define ERASE_ALIGNMENT 0x1000U
#define TABLE_ALIGNMENT 0x1000U
+#define TABLE_L2_SIZE_MAX 0x400
#define BLOB_ALIGNMENT 0x100U
#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
--
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