coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 20: (1 comment) File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/8139250c_9ca8e976?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > I was able to write it in depthcharge for an older version of the kernel . […] >>>>>>Then, it would be good to boot with a static configuration which is safest and generically applicable. pl4 with a static value of 20watts increases boot time by 40ms for warm boot and 22msec for booting from G3 for 65 watts (default adaptor).please let me know if we should have a static or a dynamic configuration based on charger. I have attached the xl sheet in the crosbug -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 20 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 10:57:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new BIT_32(x) macro.
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 11: (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/1f784eb3_20f6581b?us… : PS5, Line 27: > Hit an issue again with `BIT32` src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h:432:10: error: 'BIT32' macro redefined [-Werror,-Wmacro-redefined] > 432 | #define BIT32 0x0000000100000000ULL > | ^ > src/include/types.h:25:9: note: previous definition is here > 25 | #define BIT32(x) (1u << (x)) > | ^ how about `SET_32_BIT_FLAG` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 11 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 10:00:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
by Subrata Banik (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 10 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 09:57:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: src/include: Introducing a new BIT_32(x) macro.
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 11: (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/d19268c6_24f5bd0d?us… : PS5, Line 27: > Sure, using `BIT32` to avoid redefinition error. Hit an issue again with `BIT32` src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h:432:10: error: 'BIT32' macro redefined [-Werror,-Wmacro-redefined] 432 | #define BIT32 0x0000000100000000ULL | ^ src/include/types.h:25:9: note: previous definition is here 25 | #define BIT32(x) (1u << (x)) | ^ -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 11 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 09:33:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84174/comment/d121830d_97b0978a?us… : PS9, Line 7: src/ > please don't use `src` in the commit msg. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 9 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 09:31:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84174?usp=email to look at the new patch set (#10). Change subject: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro ...................................................................... include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro Details: - Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/cpu/x86/msr.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 10 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new BIT_32(x) macro.
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 10: (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/3f3ca9ba_51efa59c?us… : PS5, Line 27: > > Acknowledged […] Sure, using `BIT32` to avoid redefinition error. -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 10 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Sep 2024 09:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83798?usp=email to look at the new patch set (#78). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi.c A src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/cpu.c A src/soc/intel/pantherlake/crashlog.c A src/soc/intel/pantherlake/cse_telemetry.c A src/soc/intel/pantherlake/elog.c A src/soc/intel/pantherlake/finalize.c A src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/gspi.c A src/soc/intel/pantherlake/i2c.c A src/soc/intel/pantherlake/include/soc/cpu.h A src/soc/intel/pantherlake/include/soc/crashlog.h A src/soc/intel/pantherlake/include/soc/dptf.h M src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/irq.h A src/soc/intel/pantherlake/include/soc/itss.h A src/soc/intel/pantherlake/include/soc/nvs.h M src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pcie.h M src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/ramstage.h A src/soc/intel/pantherlake/include/soc/serialio.h M src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/include/soc/tcss.h A src/soc/intel/pantherlake/include/soc/usb.h A src/soc/intel/pantherlake/lockdown.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/pcie_rp.c A src/soc/intel/pantherlake/pmc.c A src/soc/intel/pantherlake/pmutil.c A src/soc/intel/pantherlake/retimer.c A src/soc/intel/pantherlake/smihandler.c A src/soc/intel/pantherlake/soundwire.c A src/soc/intel/pantherlake/spi.c A src/soc/intel/pantherlake/systemagent.c A src/soc/intel/pantherlake/tcss.c A src/soc/intel/pantherlake/uart.c A src/soc/intel/pantherlake/xhci.c 42 files changed, 3,743 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/78 -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 78 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introducing a new BIT_32(x) macro.
by Saurabh Mishra (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Saurabh Mishra. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84142?usp=email to look at the new patch set (#11). Change subject: src/include: Introducing a new BIT_32(x) macro. ...................................................................... src/include: Introducing a new BIT_32(x) macro. This new macro addition ensures the shift operation does not exceed the 32-bit width of the GEN_PMCON_A register. Details- On a 64-bit system, 1ul will typically be 64 bits wide. The left shift can accommodate values of x up to 63 without overflowing. But `GEN_PMCON_A` register width is 32-bit hence, adding new BIT_32(x) to limit the register to max 32-bit width. Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/types.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 11 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Update touchscreen power sequence
by Tongtong Pan (Code Review) 03 Sep '24

03 Sep '24

Attention is currently required from: Weimin Wu. Hello Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84196?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/dedede/var/awasuki: Update touchscreen power sequence ...................................................................... mb/google/dedede/var/awasuki: Update touchscreen power sequence Reduce resume time. BUG=b:361728839 TEST=emerge-dedede coreboot chromeos-bootimage & test touchscreen function on awasuki DUT Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/awasuki/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84196/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d Gerrit-Change-Number: 84196 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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