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Change subject: soc/intel/common/systemagent: Fixup systemagent address
......................................................................
soc/intel/common/systemagent: Fixup systemagent address
System agent in Intel common block (1) assumes TOLUD and TOUUD
registers hold the max available address plus 1, but on some SoC like
Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD
and TSEG registers to 1 MiB default, but some SoC may have different
alignments. This patch add a new function
soc_systemagent_fixup_address() to improve it.
Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 38 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/16
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Change subject: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
......................................................................
Patch Set 2: Code-Review+2
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Change subject: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries
......................................................................
Patch Set 2: Code-Review+2
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Change subject: 3rdparty/blobs/mb/google/zork: Update PSP signing token
......................................................................
Patch Set 2: Code-Review+2
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Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
Patch Set 3: Code-Review+2
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Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84197/comment/c7fec7fe_66ac1b51?us… :
PS1, Line 1: Parent: b9a12911 (mb/lattepanda: Add support for LattePanda Mu)
> I would add a note stating which commit the extra acpigen_pop_len() call was added, in gerrit's pref […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
drivers/i2c/generic: Remove erroneous acpigen_pop_len
There are one too many acpigen_pop_len calls in the code
to generate the ROTM; remove one to fix an EMERG warning.
The extra acpigen_pop_len() call was added commit
45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package").
Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/i2c/generic/generic.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84197/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84197?usp=email
to look at the new patch set (#2).
Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
drivers/i2c/generic: Remove erroneous acpigen_pop_len
There are one too many acpigen_pop_len calls in the code
to generate the ROTM; remove one to fix an EMERG warning.
The extra acpigen_pop_len() call was added commit
45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package").
Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/i2c/generic/generic.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84197/2
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Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
......................................................................
Patch Set 14:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84142/comment/ccc67e10_2ee9985a?us… :
PS14, Line 7: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
Remove the . at the end of line.
https://review.coreboot.org/c/coreboot/+/84142/comment/459f8048_7525b605?us… :
PS14, Line 9: This new macro addition ensures the shift operation does not
This is a generic macro. Please describe the macro here.
For example "This commit introduces the SET_32_BIT_FLAG macro, which generates a 32-bit mask with a specified bit set."
In subsequent lines, the GEN_PMCON_A context is explained in detail.
https://review.coreboot.org/c/coreboot/+/84142/comment/5b44c925_7ab4383a?us… :
PS14, Line 12: On a 64-bit system, 1ul will typically be 64 bits wide.
: The left shift can accommodate values of x up to 63 without overflowing.
: But `GEN_PMCON_A` register width is 32-bit hence, adding new SET_32_BIT_FLAG(x)
: to limit the register to max 32-bit width.
> is this > 72 ?
yes
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