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Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84197?usp=email )
Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84197/comment/795d6842_5a0b823d?us… :
PS1, Line 1: Parent: b9a12911 (mb/lattepanda: Add support for LattePanda Mu)
I would add a note stating which commit the extra acpigen_pop_len() call was added, in gerrit's preferred format:
commit 45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package")
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Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
......................................................................
Patch Set 14: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84142/comment/c9c7207e_7dd11cd9?us… :
PS14, Line 12: On a 64-bit system, 1ul will typically be 64 bits wide.
: The left shift can accommodate values of x up to 63 without overflowing.
: But `GEN_PMCON_A` register width is 32-bit hence, adding new SET_32_BIT_FLAG(x)
: to limit the register to max 32-bit width.
is this > 72 ?
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
......................................................................
src/include: Introducing a new SET_32_BIT_FLAG(x) macro.
This new macro addition ensures the shift operation does not
exceed the 32-bit width of the GEN_PMCON_A register.
On a 64-bit system, 1ul will typically be 64 bits wide.
The left shift can accommodate values of x up to 63 without overflowing.
But `GEN_PMCON_A` register width is 32-bit hence, adding new SET_32_BIT_FLAG(x)
to limit the register to max 32-bit width.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/include/types.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/14
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 20:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/3341ade0_66f39fc1?us… :
PS19, Line 57: * PL4 calculations - For USB C charger (Max Power):
> >>>>>>Then, it would be good to boot with a static configuration which is safest and generically applicable.
> pl4 with a static value of 20watts increases boot time by 40ms for warm boot and 22msec for booting from G3 for 65 watts (default adaptor).please let me know if we should have a static or a dynamic configuration based on charger.
> I have attached the xl sheet in the crosbug
do you know the reason behind boot time regression with static value. at what phase of the boot, you have noticed this boot regression ?
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Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84197?usp=email )
Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
Set Ready For Review
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84142?usp=email
to look at the new patch set (#13).
Change subject: src/include: Introducing a new BIT_32(x) macro.
......................................................................
src/include: Introducing a new BIT_32(x) macro.
This new macro addition ensures the shift operation does not
exceed the 32-bit width of the GEN_PMCON_A register.
On a 64-bit system, 1ul will typically be 64 bits wide.
The left shift can accommodate values of x up to 63 without overflowing.
But `GEN_PMCON_A` register width is 32-bit hence, adding new BIT_32(x)
to limit the register to max 32-bit width.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/include/types.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84142/13
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