coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... Patch Set 83: (1 comment) File src/soc/intel/pantherlake/include/soc/meminit.h: https://review.coreboot.org/c/coreboot/+/83635/comment/c14850d9_98b768d3?us… : PS83, Line 10: enum mem_type { : MEM_TYPE_LP5X, : }; : we need to have below macro inside meminit.h to support other PTLRVPs with DDR5? ``` enum mem_type { MEM_TYPE_DDR5, MEM_TYPE_LP5X, }; struct mem_ddr_config { /* Dqs Pins Interleaved Setting. Enable/Disable Control */ bool dq_pins_interleaved; }; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 83 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:28:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/ifdtool: Exit with failure on unrecognized flags
by Hsuan-ting Chen (Code Review) 09 Sep '24

09 Sep '24

Hsuan-ting Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84260?usp=email ) Change subject: util/ifdtool: Exit with failure on unrecognized flags ...................................................................... util/ifdtool: Exit with failure on unrecognized flags ifdtool will exit with success while encountering an unrecognized flag. For example, -g is a newly introduced flag, when we want to call it with an older version of ifdtool, we will get the return value 0 and cause confusion. This patch change the exit status for unrecognized flags and doesn't change the exit status for -h and -?. BUG=b:362983041 BRANCH=none TEST=futility update --servo --image /var/tmp/image.bin --quirks unlock_csme on the servo host with old ifdtool Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com> Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 --- M util/ifdtool/ifdtool.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/84260/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 Gerrit-Change-Number: 84260 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 104: (2 comments) File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/3d5a188d_36e54a5f?us… : PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB) > I am not familiar with this but start looking into this. I'm asking to add below code without any macro guarding ``` https://review.coreboot.org/c/coreboot/+/84183 ``` File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/ee64c890_ac7cf217?us… : PS104, Line 5: #include <soc/itss.h> please follow https://review.coreboot.org/c/coreboot/+/84183 -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 104 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:26:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: ifdtool: Exit with failure on unrecognized flags
by Hsuan-ting Chen (Code Review) 09 Sep '24

09 Sep '24

Hsuan-ting Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84260?usp=email ) Change subject: ifdtool: Exit with failure on unrecognized flags ...................................................................... ifdtool: Exit with failure on unrecognized flags ifdtool will exit with success while encountering an unrecognized flag. For example, -g is a newly introduced flag, when we want to call it with an older version of ifdtool, we will get the return value 0 and cause confusion. This patch change the exit status for unrecognized flags and doesn't change the exit status for -h and -?. BUG=b:362983041 BRANCH=none TEST=futility update --servo --image /var/tmp/image.bin --quirks unlock_csme on the servo host with old ifdtool Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com> Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 --- M util/ifdtool/ifdtool.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/84260/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 32b2081..5993bfc 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -2514,10 +2514,13 @@ break; case 'h': case '?': - default: print_usage(argv[0]); exit(EXIT_SUCCESS); break; + default: + print_usage(argv[0]); + exit(EXIT_FAILURE); + break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 Gerrit-Change-Number: 84260 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO high range
by Lean Sheng Tan (Code Review) 09 Sep '24

09 Sep '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Reserve MMIO high range ...................................................................... soc/intel/xeon_sp: Reserve MMIO high range Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonging to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. For example, in SPR-XCC where only CPM0/HQM0 are supported and instantiated to PCIe domains, MMIO ranges are still reserved for CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 6 files changed, 51 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 3472d58..aac5589 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -141,3 +141,8 @@ { return 0; } + +bool get_mmio_high_base_size(resource_t *base, resource_t *size) +{ + return false; +} diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c index a65e5fc..7ea65c2 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_util.c +++ b/src/soc/intel/xeon_sp/gnr/soc_util.c @@ -148,3 +148,8 @@ { return true; } + +bool get_mmio_high_base_size(resource_t *base, resource_t *size) +{ + return false; +} diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index e694af3..a7b98f3 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -31,4 +31,6 @@ union p2sb_bdf soc_get_hpet_bdf(void); union p2sb_bdf soc_get_ioapic_bdf(void); +bool get_mmio_high_base_size(resource_t *base, resource_t *size); + #endif diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 0ccacfb..0938260 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -214,3 +214,8 @@ { return 0; } + +bool get_mmio_high_base_size(resource_t *base, resource_t *size) +{ + return false; +} diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 5845327..6dd06ac 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -188,3 +188,12 @@ */ return (mem_type < MemTypeCxlAccVolatileMem); } + +bool get_mmio_high_base_size(resource_t *base, resource_t *size) +{ + const IIO_UDS *hob = get_iio_uds(); + *base = hob->PlatformData.PlatGlobalMmio64Base; + *size = hob->PlatformData.PlatGlobalMmio64Limit - (*base) + 1; + + return true; +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 2e5023d..be5b38f 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -151,6 +151,9 @@ pci_write_config32(dev, VTD_LTDPR, dpr.raw); } +#define MC_DRAM_RESOURCE_MMIO_HIGH 0x1000 +#define MC_DRAM_RESOURCE_ANON_START 0x1001 + /* * Host Memory Map: * @@ -350,7 +353,7 @@ static void mmapvtd_read_resources(struct device *dev) { - int index = 0; + int index = MC_DRAM_RESOURCE_ANON_START; /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -362,13 +365,33 @@ mc_add_dram_resources(dev, &index); } +static void mmapvtd_set_resources(struct device *dev) +{ + /* + * The MMIO high window has to be added in set_resources() instead of + * read_resources(). Because adding in read_resources() would cause the + * whole window to be reserved, and it couldn't be used for resource + * allocation. + */ + if (is_domain0(dev->upstream->dev)) { + resource_t mmio64_base, mmio64_size; + if (get_mmio_high_base_size(&mmio64_base, &mmio64_size)) { + assert(!probe_resource(dev, MC_DRAM_RESOURCE_MMIO_HIGH)); + fixed_mem_range_flags(dev, MC_DRAM_RESOURCE_MMIO_HIGH, + mmio64_base, mmio64_size, IORESOURCE_STORED); + } + } + + pci_dev_set_resources(dev); +} + static void mmapvtd_init(struct device *dev) { } static struct device_operations mmapvtd_ops = { .read_resources = mmapvtd_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = mmapvtd_set_resources, .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/83538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Gerrit-Change-Number: 83538 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: DEMO: Add PHX2 combo entry
by Bao Zheng (Code Review) 09 Sep '24

09 Sep '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84258?usp=email ) Change subject: DEMO: Add PHX2 combo entry ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I446d315d473e67d63c3d7962aa3ea7ea66b3196d Gerrit-Change-Number: 84258 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao

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[S] Change in coreboot[main]: DEMO: Cezanne add combo entry
by Bao Zheng (Code Review) 09 Sep '24

09 Sep '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84259?usp=email ) Change subject: DEMO: Cezanne add combo entry ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ee0eac69bc5963053c0a4db5a42669044fde3f Gerrit-Change-Number: 84259 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao

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[XS] Change in coreboot[main]: DEMO:amdfwtool: both a/b. not only a
by Bao Zheng (Code Review) 09 Sep '24

09 Sep '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84257?usp=email ) Change subject: DEMO:amdfwtool: both a/b. not only a ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6c93755012b4bcf5513020e06071f67e317e992 Gerrit-Change-Number: 84257 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao

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[S] Change in coreboot[main]: DEMO:amdfwtool: Add PHX2
by Bao Zheng (Code Review) 09 Sep '24

09 Sep '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84256?usp=email ) Change subject: DEMO:amdfwtool: Add PHX2 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e33f17a5ce334aed501e4b9eb4862c63efce5a Gerrit-Change-Number: 84256 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao

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[S] Change in coreboot[main]: DEMO: Cezanne add combo entry
by Bao Zheng (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84259?usp=email to review the following change. Change subject: DEMO: Cezanne add combo entry ...................................................................... DEMO: Cezanne add combo entry Change-Id: Ie6ee0eac69bc5963053c0a4db5a42669044fde3f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.mk A src/soc/amd/cezanne/fw_rn.cfg 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84259/1 diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 2747622..e56e53b 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -228,6 +228,7 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ --location $(CONFIG_AMD_FWM_POSITION) \ + --combo-config1 "src/soc/amd/cezanne/fw_rn.cfg" \ --multilevel \ --output $@ diff --git a/src/soc/amd/cezanne/fw_rn.cfg b/src/soc/amd/cezanne/fw_rn.cfg new file mode 100644 index 0000000..136ade6 --- /dev/null +++ b/src/soc/amd/cezanne/fw_rn.cfg @@ -0,0 +1,40 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/renoir/PSP +SOC_NAME Renoir + +# type file +# PSP +AMD_PUBKEY_FILE RenoirRoot.tkn +PSPBTLDR_FILE PspBootLoader_prod_RN.sbin +PSPSECUREOS_FILE psp_os_combined_prod_RN.sbin +PSPRCVR_FILE PspRecoveryBootLoader_prod_RN.sbin +PSP_SMUFW1_SUB0_FILE SmuFirmwareRN.csbin +PSPSECUREDEBUG_FILE RenoirSecureDebug_PublicKey.bin +PSPTRUSTLETS_FILE dr_ftpm_prod_RN.csbin +PSP_SMUFW2_SUB0_FILE SmuFirmware2RN.csbin +PSP_SEC_DEBUG_FILE secure_unlock_RN.sbin +PSP_HW_IPCFG_FILE_SUB0 HwIpCfg_RN_A0.sbin +PSP_IKEK_FILE PspIkekRN.bin +#PSP_SECURE_EMPTY_FILE SecureEmptyToken.bin +PSP_SECG0_FILE security_policy_RN_FP6_AM4_PspBl.sbin +PSP_MP2FW0_FILE MP2FWRN.sbin +AMD_DRIVER_ENTRIES drv_sys_prod_RN.sbin +#PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE dr_agesa_prod_RN.sbin +PSP_ABL0_FILE AgesaBootloader_U_prod_RN_LPDDR4.csbin +VBIOS_BTLOADER_FILE VbiosBootLoader_prod.sbin +SECURE_POLICY_L1_FILE security_policy_RN_FP6_AM4_tOS.sbin +UNIFIEDUSB_FILE Unified_USB_RN.sbin +DRTMTA_FILE dr_drtm_out_prod.sbin +KEYDBBL_FILE prod_kdb_bl.bin +KEYDB_TOS_FILE prod_kdb_tos.sbin +DMCUERAMDCN21_FILE dmcu_eram_Dcn21.sbin +DMCUINTVECTORSDCN21_FILE dmcu_intvectors_Dcn21.sbin + +# BDT +PSP_PMUI_FILE_SUB0_INS1 Appb_RN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 Appb_RN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS4 Appb_RN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS4 Appb_RN_2D_Lpddr4_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin -- To view, visit https://review.coreboot.org/c/coreboot/+/84259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ee0eac69bc5963053c0a4db5a42669044fde3f Gerrit-Change-Number: 84259 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit September 2024