coreboot-gerrit September 2024

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[S] Change in coreboot[main]: mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs
by Matt DeVillier (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84261?usp=email ) Change subject: mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Gerrit-Change-Number: 84261 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 13:27:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/starbook/adl: Add USB ACPI to devicetree
by Matt DeVillier (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84263?usp=email ) Change subject: mb/starlabs/starbook/adl: Add USB ACPI to devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a Gerrit-Change-Number: 84263 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 13:27:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/starlabs/merlin: Don't report the battery serial number to ACPI
by Matt DeVillier (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83633?usp=email ) Change subject: ec/starlabs/merlin: Don't report the battery serial number to ACPI ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9 Gerrit-Change-Number: 83633 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 13:22:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/starlabs/merlin: Move the chip id check
by Matt DeVillier (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83632?usp=email ) Change subject: ec/starlabs/merlin: Move the chip id check ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3 Gerrit-Change-Number: 83632 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 13:22:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84221?usp=email ) Change subject: soc/mediatek/common: Move common GPIO definitions to gpio_defs.h ...................................................................... soc/mediatek/common: Move common GPIO definitions to gpio_defs.h BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/gpio_defs.h M src/soc/mediatek/mt8186/include/soc/gpio.h M src/soc/mediatek/mt8188/include/soc/gpio.h M src/soc/mediatek/mt8192/include/soc/gpio.h M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8196/include/soc/gpio.h 6 files changed, 69 insertions(+), 199 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/gpio_defs.h b/src/soc/mediatek/common/include/soc/gpio_defs.h new file mode 100644 index 0000000..3df624c --- /dev/null +++ b/src/soc/mediatek/common/include/soc/gpio_defs.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_GPIO_DEFS_H +#define SOC_MEDIATEK_COMMON_GPIO_DEFS_H + +#include <types.h> + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +struct gpio_val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index 4ce1e98..4b88ca9 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -10,41 +10,13 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 185 -enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - #define GPIO_ID(name) PAD_##name##_ID -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - enum { PIN(0, EINT0, 0, 13, 0x16, 0x50, I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0, @@ -603,21 +575,14 @@ RES5, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { - struct val_regs dir[7]; + struct gpio_val_regs dir[7]; uint8_t rsv00[144]; - struct val_regs dout[7]; + struct gpio_val_regs dout[7]; uint8_t rsv01[144]; - struct val_regs din[7]; + struct gpio_val_regs din[7]; uint8_t rsv02[144]; - struct val_regs mode[28]; + struct gpio_val_regs mode[28]; uint8_t rsv03[560]; uint32_t dram_pinmux_trapping; }; diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h index 916cf84..b1b4b40 100644 --- a/src/soc/mediatek/mt8188/include/soc/gpio.h +++ b/src/soc/mediatek/mt8188/include/soc/gpio.h @@ -10,40 +10,12 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 177 enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, GPIO00, 0, 6, 0x31, 0xe0, TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK, I2SIN_MCK, I2SO2_MCK, DBG_MON_A0), @@ -577,20 +549,14 @@ RES5, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; struct gpio_regs { - struct val_regs dir[7]; + struct gpio_val_regs dir[7]; uint8_t rsv00[144]; - struct val_regs dout[7]; + struct gpio_val_regs dout[7]; uint8_t rsv01[144]; - struct val_regs din[7]; + struct gpio_val_regs din[7]; uint8_t rsv02[144]; - struct val_regs mode[28]; + struct gpio_val_regs mode[28]; uint8_t rsv03[560]; uint32_t dram_pinmux_trapping; }; diff --git a/src/soc/mediatek/mt8192/include/soc/gpio.h b/src/soc/mediatek/mt8192/include/soc/gpio.h index 716a63d..4746ffd 100644 --- a/src/soc/mediatek/mt8192/include/soc/gpio.h +++ b/src/soc/mediatek/mt8192/include/soc/gpio.h @@ -5,38 +5,10 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, EINT0, 0, 9, 0x23, 0xb0, SPI6_CLK, I2S5_MCK, PWM_0, TDM_LRCK, TP_GPIO0_AO, MD_INT0, RES7), @@ -699,21 +671,14 @@ I2S6_DI, I2S8_DI, RES6, RES7), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { - struct val_regs dir[7]; + struct gpio_val_regs dir[7]; uint8_t rsv00[144]; - struct val_regs dout[7]; + struct gpio_val_regs dout[7]; uint8_t rsv01[144]; - struct val_regs din[7]; + struct gpio_val_regs din[7]; uint8_t rsv02[144]; - struct val_regs mode[28]; + struct gpio_val_regs mode[28]; uint8_t rsv03[560]; uint32_t dram_pinmux_trapping; }; diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 02c3580..dcd4c36 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -5,38 +5,10 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - -enum { PIN(0, GPIO_00, 1, 0, 0x23, 0x60, TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0, PERSTN_1, IDDIG_1P, DMIC4_CLK), @@ -470,21 +442,14 @@ RES5, RES6, DBG_MON_A13), }; -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { - struct val_regs dir[7]; + struct gpio_val_regs dir[7]; uint8_t rsv00[144]; - struct val_regs dout[7]; + struct gpio_val_regs dout[7]; uint8_t rsv01[144]; - struct val_regs din[7]; + struct gpio_val_regs din[7]; uint8_t rsv02[144]; - struct val_regs mode[28]; + struct gpio_val_regs mode[28]; uint8_t rsv03[560]; uint32_t dram_pinmux_trapping; }; diff --git a/src/soc/mediatek/mt8196/include/soc/gpio.h b/src/soc/mediatek/mt8196/include/soc/gpio.h index a60cba6..acb1055 100644 --- a/src/soc/mediatek/mt8196/include/soc/gpio.h +++ b/src/soc/mediatek/mt8196/include/soc/gpio.h @@ -10,54 +10,19 @@ #include <soc/addressmap.h> #include <soc/gpio_common.h> +#include <soc/gpio_defs.h> #include <types.h> #define GPIO_NUM 271 -enum { - MAX_GPIO_REG_BITS = 32, - MAX_GPIO_MODE_PER_REG = 8, - GPIO_MODE_BITS = 4, -}; - -struct val_regs { - uint32_t val; - uint32_t set; - uint32_t rst; - uint32_t align; -}; - struct gpio_regs { - struct val_regs dir[16]; - struct val_regs dout[16]; - struct val_regs din[16]; - struct val_regs mode[32]; + struct gpio_val_regs dir[16]; + struct gpio_val_regs dout[16]; + struct gpio_val_regs din[16]; + struct gpio_val_regs mode[32]; uint32_t dram_pinmux_trapping; }; -#define PIN(id, name, flag, bit, base, offset, \ - func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name##_ID = id, \ - PAD_##name##_FLAG = flag, \ - PAD_##name##_BIT = bit, \ - PAD_##name##_BASE = base, \ - PAD_##name##_OFFSET = offset, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -#define GPIO(name) ((gpio_t){ \ - .id = PAD_##name##_ID, \ - .flag = PAD_##name##_FLAG, \ - .bit = PAD_##name##_BIT, \ - .base = PAD_##name##_BASE, \ - .offset = PAD_##name##_OFFSET \ - }) - enum { PIN(0, EINT0, 0, 0, 0x18, 0xa0, DMIC1_CLK, RES2, SPI3_A_MO, FMI2S_B_LRCK, -- To view, visit https://review.coreboot.org/c/coreboot/+/84221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Gerrit-Change-Number: 84221 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Add an option to enable A/B recovery scheme
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/cezanne: Add an option to enable A/B recovery scheme ...................................................................... soc/amd/cezanne: Add an option to enable A/B recovery scheme Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.mk 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index abeaece..7b97ce7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -408,6 +408,12 @@ help Add psp_verstage signature token to the build & PSP Directory Table +config PSP_RECOVERY_AB + bool "Use A/B Recovery scheme" + default n + help + Enable the PSP A/B Recovery mechanism + endmenu config VBOOT diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index adbf3a6..2747622 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -182,6 +182,8 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) +OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ $(OPT_PSP_NVRAM_SIZE) \ @@ -204,6 +206,7 @@ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ + $(OPT_RECOVERY_AB) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84237?usp=email ) Change subject: mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB ...................................................................... mb/google/zork: Add Kconfig to set IGD UMA allocation via APCB Add a Kconfig choice to select the IGD UMA allocation, which selects a precompiled ACPB binary with the corresponding UMA value set. Default to the previous value (128MB) for non-ChromeOS builds, and 64MB for ChromeOS as that is the value used there. TEST=build/boot google/morphius, verify UMA size changes with selection via dxdiag tool under Windows. Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/Kconfig D src/mainboard/google/zork/data.apcb M src/mainboard/google/zork/spd/Makefile.mk A src/mainboard/google/zork/uma_128.apcb A src/mainboard/google/zork/uma_256.apcb A src/mainboard/google/zork/uma_512.apcb A src/mainboard/google/zork/uma_64.apcb 7 files changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 1fcd06b..1b38d27 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -301,4 +301,25 @@ select SAR_ENABLE select USE_SAR +choice + prompt "UMA Memory Allocation" + default ZORK_UMA_SIZE_64MB if CHROMEOS + default ZORK_UMA_SIZE_128MB + help + The amount of system memory allocated for the integrated GPU. + +config ZORK_UMA_SIZE_64MB + bool "64MB" + +config ZORK_UMA_SIZE_128MB + bool "128MB" + +config ZORK_UMA_SIZE_256MB + bool "256MB" + +config ZORK_UMA_SIZE_512MB + bool "512MB" + +endchoice + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/spd/Makefile.mk b/src/mainboard/google/zork/spd/Makefile.mk index 3e6509d..1f0b20c 100644 --- a/src/mainboard/google/zork/spd/Makefile.mk +++ b/src/mainboard/google/zork/spd/Makefile.mk @@ -5,7 +5,16 @@ APCB_SOURCES=$(foreach f, $(basename $(notdir $(SPD_SOURCES))), $(obj)/APCB_$(f).gen) # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_NAME=data.apcb +ifeq ($(CONFIG_ZORK_UMA_SIZE_64MB),y) +APCB_NAME=uma_64.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_128MB),y) +APCB_NAME=uma_128.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_256MB),y) +APCB_NAME=uma_256.apcb +else ifeq ($(CONFIG_ZORK_UMA_SIZE_512MB),y) +APCB_NAME=uma_512.apcb +endif + APCB_PATH=$(src)/mainboard/$(MAINBOARDDIR) $(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)%.hex \ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_128.apcb similarity index 97% rename from src/mainboard/google/zork/data.apcb rename to src/mainboard/google/zork/uma_128.apcb index ee12694..fd605b4 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_128.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_256.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_256.apcb index ee12694..f3bd14f 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_256.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_512.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_512.apcb index ee12694..0914c2a 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_512.apcb Binary files differ diff --git a/src/mainboard/google/zork/data.apcb b/src/mainboard/google/zork/uma_64.apcb similarity index 93% copy from src/mainboard/google/zork/data.apcb copy to src/mainboard/google/zork/uma_64.apcb index ee12694..99abf34 100644 --- a/src/mainboard/google/zork/data.apcb +++ b/src/mainboard/google/zork/uma_64.apcb Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/84237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039 Gerrit-Change-Number: 84237 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84238?usp=email ) Change subject: Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax ...................................................................... Docs/mb/starlabs/byte_adl.md: Fix embedded rST syntax MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks, not eval_rst as was previously used by recommonmark. Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84238 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/starlabs/byte_adl.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/mainboard/starlabs/byte_adl.md b/Documentation/mainboard/starlabs/byte_adl.md index d357a5a..9683821 100644 --- a/Documentation/mainboard/starlabs/byte_adl.md +++ b/Documentation/mainboard/starlabs/byte_adl.md @@ -60,7 +60,7 @@ ## Flashing coreboot -```eval_rst +```{eval-rst} +---------------------+------------+ | Type | Value | +=====================+============+ -- To view, visit https://review.coreboot.org/c/coreboot/+/84238?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748 Gerrit-Change-Number: 84238 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/getac/p470/hda_verb: Use macros instead of magic numbers
by Nicholas Chin (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Elyes Haouas. Nicholas Chin has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84246?usp=email ) Change subject: mb/getac/p470/hda_verb: Use macros instead of magic numbers ...................................................................... Patch Set 1: (9 comments) File src/mainboard/getac/p470/hda_verb.c: PS1: How did you determine these? A lot of them do not decode to the same value as the original magic numbers. https://review.coreboot.org/c/coreboot/+/84246/comment/28e4e19e_b3343c4c?us… : PS1, Line 17: AZALIA_PIN_DESC( : AZALIA_JACK, : AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, : AZALIA_MIC_IN, : AZALIA_STEREO_MONO_1_8, : AZALIA_COLOR_UNKNOWN, : AZALIA_NO_JACK_PRESENCE_DETECT, : 1, 0 : ) Any configs like `0x411111fn` should be replaced with `AZALIA_PIN_CFG_NC(n)` https://review.coreboot.org/c/coreboot/+/84246/comment/1742d45b_63ddac62?us… : PS1, Line 50: AZALIA_PIN_DESC( : AZALIA_JACK, : AZALIA_INTERNAL, : AZALIA_SPEAKER, : AZALIA_OTHER_ANALOG, : AZALIA_COLOR_UNKNOWN, : AZALIA_NO_JACK_PRESENCE_DETECT, : 1, 0 : ) `AZALIA_PIN_CFG_NC(0)` https://review.coreboot.org/c/coreboot/+/84246/comment/825eaf91_c11c59f4?us… : PS1, Line 108: AZALIA_CD_IN This doesn't exist? https://review.coreboot.org/c/coreboot/+/84246/comment/1bdb1658_f5cf595e?us… : PS1, Line 105: AZALIA_PIN_DESC( : AZALIA_JACK, : AZALIA_INTERNAL, : AZALIA_CD_IN, : AZALIA_OTHER_ANALOG, : AZALIA_COLOR_UNKNOWN, : AZALIA_NO_JACK_PRESENCE_DETECT, : 1, 0 : ) `AZALIA_PIN_CFG_NC(0)` https://review.coreboot.org/c/coreboot/+/84246/comment/29e834c6_53f8ad61?us… : PS1, Line 119: AZALIA_BEEP This doesn't exist? https://review.coreboot.org/c/coreboot/+/84246/comment/a1c035ae_a1b3fed4?us… : PS1, Line 116: AZALIA_PIN_DESC( : AZALIA_INTEGRATED, : AZALIA_INTERNAL, : AZALIA_BEEP, : AZALIA_OTHER_ANALOG, : AZALIA_COLOR_UNKNOWN, : AZALIA_NO_JACK_PRESENCE_DETECT, : 1, 0 : ) `AZALIA_PIN_CFG_NC(0)` https://review.coreboot.org/c/coreboot/+/84246/comment/fde8d00d_fda9bf06?us… : PS1, Line 127: AZALIA_PIN_DESC( : AZALIA_JACK, : AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_REAR, : AZALIA_DIGITAL_OUT, : AZALIA_OTHER_DIGITAL, : AZALIA_BLACK, : AZALIA_JACK_PRESENCE_DETECT, : 1, 0 : ) `AZALIA_PIN_CFG_NC(0)` https://review.coreboot.org/c/coreboot/+/84246/comment/8cd17981_006d60eb?us… : PS1, Line 138: AZALIA_PIN_DESC( : AZALIA_JACK, : AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_FRONT, : AZALIA_DIGITAL_IN, : AZALIA_OTHER_DIGITAL, : AZALIA_BLACK, : AZALIA_JACK_PRESENCE_DETECT, : 1, 0 : ) `AZALIA_PIN_CFG_NC(0)` -- To view, visit https://review.coreboot.org/c/coreboot/+/84246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I247ac1ae88a623489a98e876ea10d8515b6f3e9d Gerrit-Change-Number: 84246 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 09 Sep 2024 12:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: Doc/rmodules.md: Change header levels
by Nicholas Chin (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Nico Huber. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84239?usp=email ) Change subject: Doc/rmodules.md: Change header levels ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Looks like this got mixed with CB:84245? Good catch. Fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 09 Sep 2024 12:08:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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