coreboot-gerrit September 2024

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[S] Change in coreboot[main]: Doc/rmodules.md: Change header levels
by Nicholas Chin (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Nicholas Chin, Nico Huber. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84239?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: Doc/rmodules.md: Change header levels ...................................................................... Doc/rmodules.md: Change header levels Increase the header levels of headers following the initial "Relocatable Modules (rmodules)" so that there is only one title for the page with the other headings as subheadings. Also fix header capitalization while we're here. Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/rmodules.md 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/84239/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 104: (13 comments) Patchset: PS104: me File src/soc/intel/common/block/acpi/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/3cbd670c_58857b78?us… : PS104, Line 284: Name (_UID, 1) please submit this CL separately File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/42f01c84_df3ae1c5?us… : PS104, Line 3: #define R_ICLK_PCR_CAMERA1 0x8000 : #define B_ICLK_PCR_FREQUENCY 0x1 : #define B_ICLK_PCR_REQUEST 0x2 : can you please point me at the EDS section to compare the bit-field? I could see different macros are being used across different SoC. ``` grep -rsn "B_ICLK_PCR_FREQUENCY" src/soc/intel/ src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl:4:#define B_ICLK_PCR_FREQUENCY 0x1 src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl:40: RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl:4:#define B_ICLK_PCR_FREQUENCY 0x1 src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl:51: RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) src/soc/intel/alderlake/acpi/camera_clock_ctl.asl:4:#define B_ICLK_PCR_FREQUENCY 0x1 src/soc/intel/alderlake/acpi/camera_clock_ctl.asl:40: RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) src/soc/intel/meteorlake/acpi/camera_clock_ctl.asl:4:#define B_ICLK_PCR_FREQUENCY 0x3 src/soc/intel/meteorlake/acpi/camera_clock_ctl.asl:44: RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl:4:#define B_ICLK_PCR_FREQUENCY 0x1 src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl:52: RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) ``` File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/ad95da09_c55ace64?us… : PS104, Line 396: /*OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)*/ do we need this ? https://review.coreboot.org/c/coreboot/+/83772/comment/67fddb7d_aa9886dd?us… : PS104, Line 779: If (TRE2 == 1) { same https://review.coreboot.org/c/coreboot/+/83772/comment/25ddaab3_eb511bdd?us… : PS104, Line 809: If (TRE3 == 1) { again same problem, this PTL code is so old that you need to rebase to apply latest code changes. Refer to https://review.coreboot.org/c/coreboot/+/81842 File src/soc/intel/pantherlake/acpi/tcss_dma.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/4f6e70fc_feb606c9?us… : PS104, Line 13: 0xC8 use smallcase `0xc8` https://review.coreboot.org/c/coreboot/+/83772/comment/202d20f1_14744141?us… : PS104, Line 22: Offset (0xFF), : DMAD, 8 /* 31:24 DMA Active Delay */ can you please point me at EDS chapter ? File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/efb47b3f_b82eede4?us… : PS23, Line 56: 0xBAC > Subrata, I browsed across the ASL files and check how the Field under OperationRegion are written, the Offset always uses with direct value instead of macros. I assume you mean all the hard-coded offset value and not just this particular one. Unless the same offset has been used in multiple places, I'd rather leave it as it for consistency reason. In addition, the ASL will look closer to its converted .dsl file from the platform for debug/comparison purpose. Will it be okay? a macro is desired to explain the purpose, preferably register name. for example: 1. 0xBB2 <---- Root Port Power Gating Enable = TCSS_CFG_RPPGEN_FROM_CCFG File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/f7052859_78a8b331?us… : PS104, Line 22: Offset (0x5B), we don't need this line https://review.coreboot.org/c/coreboot/+/83772/comment/0b95114b_57d8ddbb?us… : PS104, Line 15: Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */ : ABPX, 1, /* 0, Attention Button Pressed */ : , 2, : PDCX, 1, /* 3, Presence Detect Changed */ : , 2, : PDSX, 1, /* 6, Presence Detect State */ : , 1, : Offset (0x5B), : DLSC, 1, /* 8, Data Link Layer State Changed */ why not this? ``` Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */ ABPX, 1, /* 0, Attention Button Pressed */ , 2, PDCX, 1, /* 3, Presence Detect Changed */ , 2, PDSX, 1, /* 6, Presence Detect State */ , 1, DLSC, 1, /* 8, Data Link Layer State Changed */ ``` https://review.coreboot.org/c/coreboot/+/83772/comment/d0dd931b_5b9706c7?us… : PS104, Line 24: Offset(0x60), /* RSTS - Root Status Register */ : Offset(0x62), why not ``` Offset(0x60), /* RSTS - Root Status Register */ , 16, ``` https://review.coreboot.org/c/coreboot/+/83772/comment/18de563d_a1fcef0c?us… : PS104, Line 32: Offset (0x404), : LSOE, 1, : LNSE, 1, i don't see the register definition is part of EDS -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 104 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 10:26:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 93: (26 comments) File src/soc/intel/pantherlake/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83798/comment/c24c5f21_aecb670a?us… : PS93, Line 21: bootblock-y += gpio.c can u please drop this now ? knowing line 15 already added those files ? https://review.coreboot.org/c/coreboot/+/83798/comment/87528a33_68f01851?us… : PS93, Line 26: romstage-y += gpio.c can u please drop this now ? knowing line 15 already added those files ? File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/cc54038b_69b9dc64?us… : PS93, Line 25: #define GFXVT_ENABLED BIT(0) : #define NONGFXVT_ENABLED BIT(1) : #define IOCVT_ENABLED BIT(2) please move macro definitions under `soc/intel/pantherlake/include/soc/systemagent.h` ``` #define GFXVTBAR VTDBAR #define GFXVT_ENABLED BIT(0) #define NONGFXVT_ENABLED BIT(1) #define IOCVT_ENABLED BIT(2) ``` https://review.coreboot.org/c/coreboot/+/83798/comment/c48e67e3_cf7f2bd1?us… : PS93, Line 123: initialized nit: then you don't need to use a comment to explain (line 123 and 148) `c_state_initialized` https://review.coreboot.org/c/coreboot/+/83798/comment/d3ff48bf_1e958c8e?us… : PS93, Line 123: int why not `bool`? https://review.coreboot.org/c/coreboot/+/83798/comment/fbf579af_e11053a5?us… : PS93, Line 190: tab File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/82b4021f_608382ed?us… : PS93, Line 339: heci_enabled who is the consumer or who is expected to be the consumer of this code? https://review.coreboot.org/c/coreboot/+/83798/comment/c5399c77_ec21bfc8?us… : PS93, Line 522: pch_usb_oc_enable who is the consumer? File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/d245fd28_bcf2346a?us… : PS93, Line 21: #include <soc/itss.h> why we need this ? refer to https://review.coreboot.org/c/coreboot/+/84183 https://review.coreboot.org/c/coreboot/+/83798/comment/a312b72a_041d2895?us… : PS93, Line 115: case PCI_DEVFN_SPI: return "FSPI"; is this required ? File src/soc/intel/pantherlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/83798/comment/a5190198_f433684f?us… : PS93, Line 12: please be consistent with tab or space https://review.coreboot.org/c/coreboot/+/83798/comment/bd650f14_2b8a819e?us… : PS93, Line 18: same as above File src/soc/intel/pantherlake/cpu.c: https://review.coreboot.org/c/coreboot/+/83798/comment/21df6bc6_0599806d?us… : PS93, Line 59: /* Fast String enable */ with introduction of the macro, I felt these comments are redundant ones, https://review.coreboot.org/c/coreboot/+/83798/comment/5f58e8e3_6757d2af?us… : PS93, Line 126: const config_t *conf = config_of_soc(); : if (conf == NULL) { : printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); : return; : } : /* Set energy-performance preference */ : if (conf->enable_energy_perf_pref) : if (check_energy_perf_cap()) : set_energy_perf_pref(conf->energy_perf_pref_value); : looks like returning from this function won't be appropriate looking at remaining operations like enabling turbo etc. (those are not dependent over config). Therefore, I would suggest using below logic. ``` const config_t *conf = config_of_soc(); /* Set energy-performance preference */ if (conf != NULL && conf->enable_energy_perf_pref) { if (check_energy_perf_cap()) set_energy_perf_pref(conf->energy_perf_pref_value); } ``` https://review.coreboot.org/c/coreboot/+/83798/comment/5ffd4617_e9fa9856?us… : PS93, Line 144: empty line. https://review.coreboot.org/c/coreboot/+/83798/comment/59c1eb2b_83765cde?us… : PS93, Line 144: Add a TODO to add support for DROP_CPU_FEATURE_PROGRAM_IN_FSP File src/soc/intel/pantherlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/cc71be2d_f0a33767?us… : PS93, Line 18: SoC-N there is no SoC die. Please confirm if this node count is appropriate for PTL File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/34130392_497fb58c?us… : PS93, Line 12: #include <stdint.h> drop this , seems not required File src/soc/intel/pantherlake/finalize.c: https://review.coreboot.org/c/coreboot/+/83798/comment/9b92bd59_0f626725?us… : PS93, Line 7: #include <delay.h> do we need this ? https://review.coreboot.org/c/coreboot/+/83798/comment/e937687c_6f180997?us… : PS93, Line 28: static void pch_handle_sideband(config_t *config) : { : : } can you please follow https://review.coreboot.org/c/coreboot/+/84189 ? File src/soc/intel/pantherlake/include/soc/dptf.h: https://review.coreboot.org/c/coreboot/+/83798/comment/1bbc7c29_46624ae9?us… : PS93, Line 6: /* Below are the unique ACPI Device IDs for thermal/dptf on SoC. */ this is not a complete sentence IMO. can you please help to rewrite ? File src/soc/intel/pantherlake/include/soc/itss.h: https://review.coreboot.org/c/coreboot/+/83798/comment/7fbc2bde_e00b1aac?us… : PS93, Line 3: TSS_H please follow https://review.coreboot.org/c/coreboot/+/84183 File src/soc/intel/pantherlake/pcie_rp.c: https://review.coreboot.org/c/coreboot/+/83798/comment/d71d322c_a83c458f?us… : PS93, Line 3: #include <console/console.h> i don't see a need for console here ? File src/soc/intel/pantherlake/pmc.c: https://review.coreboot.org/c/coreboot/+/83798/comment/cd132a89_4ee25c2e?us… : PS93, Line 27: Pmc PMC in all capital https://review.coreboot.org/c/coreboot/+/83798/comment/7c8baebb_61b171eb?us… : PS93, Line 27: mmio MMIO File src/soc/intel/pantherlake/retimer.c: https://review.coreboot.org/c/coreboot/+/83798/comment/fb8c46dc_6a1ef1d6?us… : PS93, Line 7: #include <soc/soc_info.h> drop this, not needed it seems -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 93 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Doc/rmodules.md: Move to lib
by Nico Huber (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84240?usp=email ) Change subject: Doc/rmodules.md: Move to lib ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c Gerrit-Change-Number: 84240 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Doc/rmodules.md: Change header levels
by Nico Huber (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84239?usp=email ) Change subject: Doc/rmodules.md: Change header levels ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Looks like this got mixed with CB:84245? -- To view, visit https://review.coreboot.org/c/coreboot/+/84239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811 Gerrit-Change-Number: 84239 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/ifdtool: Exit with failure on unrecognized flags
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Hsuan-ting Chen, Reka Norman. Subrata Banik has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/coreboot/+/84260?usp=email ) Change subject: util/ifdtool: Exit with failure on unrecognized flags ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067 Gerrit-Change-Number: 84260 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:34:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/starbook/adl: Add USB ACPI to devicetree
by Sean Rhodes (Code Review) 09 Sep '24

09 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84263?usp=email ) Change subject: mb/starlabs/starbook/adl: Add USB ACPI to devicetree ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a Gerrit-Change-Number: 84263 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:34:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Remove PMC GPIO routing
by Sean Rhodes (Code Review) 09 Sep '24

09 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84262?usp=email ) Change subject: mb/starlabs/starbook/adl: Remove PMC GPIO routing ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf Gerrit-Change-Number: 84262 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:34:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs
by Sean Rhodes (Code Review) 09 Sep '24

09 Sep '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84261?usp=email ) Change subject: mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0 Gerrit-Change-Number: 84261 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 09:34:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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