coreboot-gerrit September 2024

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84104/comment/762b1e16_f57edbf2?us… : PS11, Line 241: gpe0_mask > > shouldn't this be gpe1_mask? same below […] it is gpe0_mask indeed, as all GPE1 events are finer granularity of some GPE0 events, which included TCSS/non-TCSS PME_B0, hot plug, PCIe events. For instance, if GPE0 PME_EN is disabled, the [internal device]_PME_EN bits will also needs to be disabled. Same thing apply to hot plug and PCIe events. There is no additional types of event added in GPE1. The purpose of GPE1 events is for performance matter. Instead of waking up all device and finding out which one is the event source. GPE1 events is checked directly. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 09 Sep 2024 16:21:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: make same cpu pyhsical address
by Jérémy Compostella (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Jamie Ryu, Lance Zhao, Tim Wawrzynczak, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/84230?usp=email ) Change subject: make same cpu pyhsical address ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: If I remember well, CPU Physical Address size and SoC physic Address size can be different. Like on MTL CPU Phisical Address size is 46 but only 42 can be used at the SoC level. This is the reason we introduced this difference in the coreboot code. -- To view, visit https://review.coreboot.org/c/coreboot/+/84230?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 Gerrit-Change-Number: 84230 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 16:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: edid.h: Increase EDID_ASCII_STRING_LENGTH to 14
by Elyes Haouas (Code Review) 09 Sep '24

09 Sep '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84277?usp=email ) Change subject: edid.h: Increase EDID_ASCII_STRING_LENGTH to 14 ...................................................................... edid.h: Increase EDID_ASCII_STRING_LENGTH to 14 This fixes following errors (using GCC-15): CC+STRIP src/drivers/mipi/panel-KD_KD101NE3_40TI.c CC+STRIP src/drivers/mipi/panel-LCE_LMFBX101117480.c src/drivers/mipi/panel-LCE_LMFBX101117480.c:7:33: error: initializer-string for array of 'char' is too long [-Werror=unterminated-string-initialization] 7 | .ascii_string = "LMFBX101117480", | ^~~~~~~~~~~~~~~~ Change-Id: I48196ba7f7cd8520dbf7f62385b7d83012ad617f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/edid.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84277/1 diff --git a/src/include/edid.h b/src/include/edid.h index b2d6aa2..a21609e 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -44,7 +44,7 @@ * unsigned int. We can move more into this struct as needed. */ -#define EDID_ASCII_STRING_LENGTH 13 +#define EDID_ASCII_STRING_LENGTH 14 struct edid { /* These next three things used to all be called bpp. -- To view, visit https://review.coreboot.org/c/coreboot/+/84277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48196ba7f7cd8520dbf7f62385b7d83012ad617f Gerrit-Change-Number: 84277 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Subrata Banik. Felix Held has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: PS11: > > are the gpe1 registers for the same event as the gpe0 register with the same number? the code usin […] so i'd guess that it's not correct to use the identical mask pmc_enable_std_gpe and pmc_disable_std_gpe to enable/disable the GPE0 and GPE1 https://review.coreboot.org/c/coreboot/+/84104/comment/1b37ef77_afbebd8b?us… : PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */ : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a) : { : return NULL; : } : : /* disable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask) : { : } : : /* enable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask) : { : } > > are those weak functions needed? i'd assume that if a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE […] when a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, it has to implement those 3 functions in the soc code; when a soc doesn't select SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, all calls of those functions get optimized out, so i don't think that there's the need to have a weak implementation of those -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 15:46:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: PS11: > are the gpe1 registers for the same event as the gpe0 register with the same number? the code using the same masks for the gpe0 and gpe1 suggest that to me, but i have some doubts that this is actually the case no, GPE events can't be generalized like GPE0 events, this is some SoC specific depending upon the internal IPs https://review.coreboot.org/c/coreboot/+/84104/comment/98257a33_f2ea5f0c?us… : PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */ : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a) : { : return NULL; : } : : /* disable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask) : { : } : : /* enable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask) : { : } > are those weak functions needed? i'd assume that if a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, it needs to implement those and if it doesn't select that option, those function implementations won't be needed. we need to implement those weak function to provide the lists of GPE1 event as this is soc specific -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 09 Sep 2024 15:35:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Felix Held has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 11: (4 comments) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84104/comment/69d5a39a_643c18f7?us… : PS11, Line 239: based on standard GPE0 EN bits hmm, this sounds odd to me https://review.coreboot.org/c/coreboot/+/84104/comment/ecda8374_54345401?us… : PS11, Line 241: gpe0_mask shouldn't this be gpe1_mask? same below File src/soc/intel/common/block/pmc/pmclib.c: PS11: are the gpe1 registers for the same event as the gpe0 register with the same number? the code using the same masks for the gpe0 and gpe1 suggest that to me, but i have some doubts that this is actually the case https://review.coreboot.org/c/coreboot/+/84104/comment/b5a20cdb_29759aed?us… : PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */ : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a) : { : return NULL; : } : : /* disable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask) : { : } : : /* enable the corresponding GPE1 bits based on standard GPE0 bits */ : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask) : { : } are those weak functions needed? i'd assume that if a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, it needs to implement those and if it doesn't select that option, those function implementations won't be needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 15:13:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Cliff Huang. Felix Held has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/84103/comment/f0a82554_c1c0c50b?us… : PS15, Line 110: fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : 0; : if (fadt->gpe1_blk) { checking if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) is true and if so setting the 3 values within that if block would make the code easier to read -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 15 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Mon, 09 Sep 2024 15:11:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/cbfstool: Print max empty entry size in error message
by Felix Held (Code Review) 09 Sep '24

09 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84204?usp=email ) Change subject: util/cbfstool: Print max empty entry size in error message ...................................................................... util/cbfstool: Print max empty entry size in error message Currently, cbfstool prints the following error message when the added file doesn't fit in the region: E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big? It requires manual inspection to know the space left in the region. To make that easier, also print the maximum empty CBFS entry size in the error message: E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0; Largest empty slot: 512 bytes Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M util/cbfstool/cbfs_image.c 1 file changed, 10 insertions(+), 4 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 740a3b2..e935357 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -743,6 +743,8 @@ uint32_t entry_type; uint32_t addr, addr_next; + uint32_t entry_size; + uint32_t max_null_entry_size = 0; struct cbfs_file *entry, *next; uint32_t need_size; uint32_t header_size = be32toh(header->offset); @@ -766,9 +768,11 @@ addr = cbfs_get_entry_addr(image, entry); next = cbfs_find_next_entry(image, entry); addr_next = cbfs_get_entry_addr(image, next); + entry_size = addr_next - addr; + max_null_entry_size = MAX(max_null_entry_size, entry_size); DEBUG("cbfs_add_entry: space at 0x%x+0x%x(%d) bytes\n", - addr, addr_next - addr, addr_next - addr); + addr, entry_size, entry_size); /* Will the file fit? Don't yet worry if we have space for a new * "empty" entry. We take care of that later. @@ -803,7 +807,7 @@ } DEBUG("section 0x%x+0x%x for content_offset 0x%x.\n", - addr, addr_next - addr, content_offset); + addr, entry_size, content_offset); if (cbfs_add_entry_at(image, entry, buffer->data, content_offset, header, len_align) == 0) { @@ -812,8 +816,10 @@ break; } - ERROR("Could not add [%s, %zd bytes (%zd KB)@0x%x]; too big?\n", - buffer->name, buffer->size, buffer->size / 1024, content_offset); + ERROR("Could not add %s [header %d + content %zd bytes (%zd KB)] @0x%x; " + "Largest empty slot: %d bytes\n", + buffer->name, header_size, buffer->size, buffer->size / 1024, content_offset, + max_null_entry_size); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661 Gerrit-Change-Number: 84204 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl: Remove PMC GPIO routing
by Matt DeVillier (Code Review) 09 Sep '24

09 Sep '24

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84262?usp=email ) Change subject: mb/starlabs/starbook/adl: Remove PMC GPIO routing ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf Gerrit-Change-Number: 84262 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 09 Sep 2024 13:27:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit September 2024