coreboot-gerrit September 2024

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[S] Change in coreboot[main]: amdfwtool: Add injection corruption to call if necessary
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84579?usp=email to review the following change. Change subject: amdfwtool: Add injection corruption to call if necessary ...................................................................... amdfwtool: Add injection corruption to call if necessary Change-Id: I5be9456ad8b76c1b6b3975248ea18306acfa3e99 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/84579/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 41214a0..ce164bc 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1017,6 +1017,9 @@ if (cb_config->debug) check_ab_recovery(ctx->pspdir2, ctx->pspdir2_b); + /* Inject corruption to PSP L2A header, Entry=0x48, Level=2 */ + if (0) + *(uint8_t *)pspdir2 = 0xFF; copy_psp_header(ctx->pspdir_bak, ctx->pspdir); } else if (pspdir2 != NULL) { @@ -1182,6 +1185,14 @@ pspdir->entries[count].addr = RUN_CURRENT(*ctx); pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); + + if (0) + /* Inject corrption to SMU. EntryId=8, level=2 */ + if (fw_table[i].type == AMD_FW_PSP_SMU_FIRMWARE && + ctx->pspdir2 != NULL && + ctx->pspdir2_b == NULL) + *(uint8_t *)BUFF_CURRENT(*ctx) = 0xFF; + adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT); } @@ -1342,6 +1353,9 @@ TABLE_L2_SIZE_MAX); if (cb_config->debug) check_ab_recovery(ctx->biosdir2, ctx->biosdir2_b); + /* Inject corrption to BIOS table header. TypeId=0x49, level=2 */ + if (0) + *(uint8_t *)ctx->biosdir2 = 0xFF; } } else if (ctx->biosdir2) { current_table_save = ctx->current_table; @@ -1549,6 +1563,14 @@ exit(1); } + /* Inject corrption to x86 reset vector, EntryId=0x62, level=2 */ + if (0) + if (ctx->biosdir2 != NULL && ctx->biosdir2_b == NULL) { + *((uint32_t *)BUFF_CURRENT(*ctx) + 0x100/4) = 0xFFFFFFFF; + *((uint32_t *)BUFF_CURRENT(*ctx) + 0x104/4) = 0xFFFFFFFF; + *((uint32_t *)BUFF_CURRENT(*ctx) + 0x108/4) = 0xFFFFFFFF; + *((uint32_t *)BUFF_CURRENT(*ctx) + 0x10C/4) = 0xFFFFFFFF; + } biosdir->entries[count].source = RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_TAB); biosdir->entries[count].address_mode = @@ -1575,6 +1597,12 @@ biosdir->entries[count].size = (uint32_t)bytes; biosdir->entries[count].source = RUN_CURRENT(*ctx); biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); + /* Inject corrption to APCB. It can not boot based on test. */ + if (0) + if (fw_table[i].type == AMD_BIOS_APCB && + ctx->biosdir2 != NULL && + ctx->biosdir2_b == NULL) + *(uint8_t *)BUFF_CURRENT(*ctx) = 0xFF; adjust_current_pointer(ctx, bytes, 0x100U); if (fw_table[i].type == AMD_BIOS_APCB && !cb_config->have_apcb_bk) { -- To view, visit https://review.coreboot.org/c/coreboot/+/84579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5be9456ad8b76c1b6b3975248ea18306acfa3e99 Gerrit-Change-Number: 84579 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

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[XS] Change in coreboot[main]: mb/amd/majolica: Call abrecovery in romstage to heal the corruption
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84578?usp=email to review the following change. Change subject: mb/amd/majolica: Call abrecovery in romstage to heal the corruption ...................................................................... mb/amd/majolica: Call abrecovery in romstage to heal the corruption Change-Id: I0e0946b9519de9f778d2f0b8c262003e00bc3fd7 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/majolica/port_descriptors.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84578/1 diff --git a/src/mainboard/amd/majolica/port_descriptors.c b/src/mainboard/amd/majolica/port_descriptors.c index 3221698..5549f7a 100644 --- a/src/mainboard/amd/majolica/port_descriptors.c +++ b/src/mainboard/amd/majolica/port_descriptors.c @@ -2,6 +2,7 @@ #include <gpio.h> #include <soc/platform_descriptors.h> +#include <soc/cpu.h> #include <types.h> #include <amdblocks/cpu.h> @@ -132,4 +133,7 @@ *dxio_num = ARRAY_SIZE(majolica_dxio_descriptors); *ddi_descs = majolica_ddi_descriptors; *ddi_num = ARRAY_SIZE(majolica_ddi_descriptors); +#if ENV_ROMSTAGE_OR_BEFORE + abrecovery(); +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/84578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e0946b9519de9f778d2f0b8c262003e00bc3fd7 Gerrit-Change-Number: 84578 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/cezanne: Heal the corruption in A/B recovery
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84577?usp=email to review the following change. Change subject: soc/amd/cezanne: Heal the corruption in A/B recovery ...................................................................... soc/amd/cezanne: Heal the corruption in A/B recovery Change-Id: I2cdab00a7122e4831fe5d91cf5d390ad11db0999 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.mk A src/soc/amd/cezanne/abrecovery.c M src/soc/amd/cezanne/include/soc/cpu.h 3 files changed, 191 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84577/1 diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 2747622..2445ed5 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -17,6 +17,7 @@ bootblock-y += espi_util.c romstage-y += fsp_m_params.c +romstage-y += abrecovery.c ramstage-y += acpi.c ramstage-y += chip.c @@ -231,6 +232,8 @@ --multilevel \ --output $@ +# --combo-config1 "src/soc/amd/cezanne/fw_rn.cfg" \ + $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/amd/cezanne/abrecovery.c b/src/soc/amd/cezanne/abrecovery.c new file mode 100644 index 0000000..868a4fc --- /dev/null +++ b/src/soc/amd/cezanne/abrecovery.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> +#include <amdblocks/cpu.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> +#include <amdblocks/psp.h> +#include <amdblocks/smn.h> +#include <arch/io.h> +#include <spi_flash.h> +#include <amdblocks/reset.h> + +#define HAVE_ISH 0 +#define DATA_SIZE 0x400 +static uint8_t readbiosram(uint8_t idx) +{ + outb(idx, 0xcd4); + return inb(0xcd5); +} + +static uint32_t get_pspl1_offset(struct spi_flash *flash, uint32_t romsig_off) +{ + uint8_t data[DATA_SIZE]; + uint32_t psp; + + spi_flash_read(flash, romsig_off, DATA_SIZE, data); + psp = *(uint32_t *)(data + 0x14); + return psp; +} + +static void get_psp_entry(struct spi_flash *flash, uint32_t psp_dir, uint8_t entry_type, uint32_t *table_offset, uint32_t *table_size) +{ + uint8_t data[DATA_SIZE]; + uint32_t entry_off = 0, index, address_mode, entry_num; + + spi_flash_read(flash, psp_dir, DATA_SIZE, data); + entry_num = *(uint8_t *)(data + 0x08); + + for (index=0; index < entry_num; index++) { + entry_off = 0x10 + index * 0x10; + if (entry_type == data[entry_off]) + break; + } + address_mode = *(uint32_t *)(data + entry_off + 0xC) & 0xC0000000; + *table_offset = *(uint32_t *)(data + entry_off + 0x8); + if (address_mode == 0x80000000) + *table_offset += psp_dir; + + *table_size = *(uint32_t *)(data + entry_off + 0x4); +} + +#if HAVE_ISH +static uint32_t get_table_size(struct spi_flash *flash, uint32_t table) +{ + uint8_t data[DATA_SIZE]; + + spi_flash_read(flash, table, DATA_SIZE, data); + return (*(uint32_t *)(data+0xC) & 0x3ff) * 0x1000;/* Here 0x1000 is not sector_size. */ +} +#endif + +static void get_bios_entry(struct spi_flash *flash, uint32_t bios_dir, uint8_t entry_type, uint32_t *table_offset, uint32_t *table_size) +{ + uint8_t data[DATA_SIZE]; + uint32_t entry_off = 0, index, address_mode, entry_num; + + spi_flash_read(flash, bios_dir, DATA_SIZE, data); + entry_num = *(uint8_t *)(data + 0x08); + + for (index=0; index < entry_num; index++) { + entry_off = 0x10 + index * 0x18; + if (entry_type == data[entry_off]) + break; + } + address_mode = *(uint32_t *)(data + entry_off + 0xc) & 0xC0000000; + *table_offset = *(uint32_t *)(data + entry_off + 0x8); + if (address_mode == 0x80000000) + *table_offset += bios_dir; + + *table_size = *(uint32_t *)(data + entry_off + 0x4); +} + +#if HAVE_ISH +static uint32_t get_l2_from_ish(struct spi_flash *flash, uint32_t ish, uint32_t ish_size) +{ + uint8_t data[DATA_SIZE]; + uint32_t psp_l2; + spi_flash_read(flash, ish, DATA_SIZE, data); + psp_l2 = *(uint32_t *)(data + 0x10); + return psp_l2; +} +#endif + +void abrecovery(void) +{ + uint32_t reason, corrupt_entryid, corrupt_level; + struct spi_flash flash; + uint8_t data[0x1000]; + uint32_t index; + uint32_t psp_dir, pspl2a_dir, pspl2b_dir, pspl2a_size, pspl2b_size; + uint32_t biosl2a_dir, biosl2b_dir, biosl2a_size, biosl2b_size; + #if HAVE_ISH + uint32_t isha_dir, isha_size, ishb_dir, ishb_size; + #endif + uint32_t corrupt_ent_off, corrupt_ent_size, backup_ent_off, backup_ent_size; + uint32_t flash_sector_size; + + if (check_abrecovery()) { + printk(BIOS_DEBUG, "recovery\n"); + } else { + printk(BIOS_DEBUG, "no recovery\n"); + return; + } + reason = readbiosram(0x78); + corrupt_entryid = reason; + printk(BIOS_DEBUG, "recovery reason byte 1=%x\n", reason); + reason = readbiosram(0x79); + printk(BIOS_DEBUG, "recovery reason byte 2=%x\n", reason); + reason = readbiosram(0x7A); + corrupt_level = reason & 3; + printk(BIOS_DEBUG, "recovery reason byte 3=%x, corrupt_level=%x\n", reason, corrupt_level); + reason = readbiosram(0x7B); + printk(BIOS_DEBUG, "recovery reason byte 4=%x\n", reason); + spi_flash_probe(0, 0, &flash); + flash_sector_size = flash.sector_size; + psp_dir = get_pspl1_offset(&flash, CONFIG_AMD_FWM_POSITION); +#if !HAVE_ISH + /* NO ISH */ + get_psp_entry(&flash, psp_dir, 0x48, &pspl2a_dir, &pspl2a_size); + get_psp_entry(&flash, psp_dir, 0x4A, &pspl2b_dir, &pspl2b_size); + printk(BIOS_DEBUG, "pspl2a_dir=%x, pspl2a_size=%x\n", pspl2a_dir, pspl2a_size); + printk(BIOS_DEBUG, "pspl2b_dir=%x, pspl2b_size=%x\n", pspl2b_dir, pspl2b_size); +#else + get_psp_entry(&flash, psp_dir, 0x48, &isha_dir, &isha_size); + get_psp_entry(&flash, psp_dir, 0x4A, &ishb_dir, &ishb_size); + printk(BIOS_DEBUG, "isha_dir=%x, isha_size=%x\n", isha_dir, isha_size); + printk(BIOS_DEBUG, "ishb_dir=%x, ishb_size=%x\n", ishb_dir, ishb_size); + pspl2a_dir = get_l2_from_ish(&flash, isha_dir, isha_size); + pspl2b_dir = get_l2_from_ish(&flash, ishb_dir, ishb_size); + printk(BIOS_DEBUG, "pspl2a_dir=%x, pspl2a_size=%x\n", pspl2a_dir, pspl2a_size); + printk(BIOS_DEBUG, "pspl2b_dir=%x, pspl2b_size=%x\n", pspl2b_dir, pspl2b_size); + pspl2a_size = get_table_size(&flash, pspl2a_dir); + pspl2b_size = get_table_size(&flash, pspl2b_dir); + printk(BIOS_DEBUG, "pspl2a_size=%x, pspl2b_size=%x\n", pspl2a_size, pspl2b_size); +#endif + get_psp_entry(&flash, pspl2a_dir, 0x49, &biosl2a_dir, &biosl2a_size); + printk(BIOS_DEBUG, "biosl2a_offset=%x, biosl2b_size=%x\n", biosl2a_dir, biosl2a_size); + get_psp_entry(&flash, pspl2b_dir, 0x49, &biosl2b_dir, &biosl2b_size); + printk(BIOS_DEBUG, "biosl2a_offset=%x, biosl2b_size=%x\n", biosl2b_dir, biosl2b_size); + + if (corrupt_entryid == 0x48 && corrupt_level == 2) { + corrupt_ent_off = pspl2a_dir; + corrupt_ent_size = ALIGN_UP(pspl2a_size, flash_sector_size); + backup_ent_off = pspl2b_dir; + backup_ent_size = ALIGN_UP(pspl2b_size, flash_sector_size); + } else if (corrupt_entryid == 0x49 && corrupt_level == 2){ + corrupt_ent_off = biosl2a_dir; + corrupt_ent_size = ALIGN_UP(biosl2a_size, flash_sector_size); + backup_ent_off = biosl2b_dir; + backup_ent_size = ALIGN_UP(biosl2b_size, flash_sector_size); + } else if (corrupt_entryid >= 0x60 && corrupt_entryid <= 0x70 && corrupt_level == 2) { + get_bios_entry(&flash, biosl2b_dir, corrupt_entryid, &backup_ent_off, &backup_ent_size); + get_bios_entry(&flash, biosl2a_dir, corrupt_entryid, &corrupt_ent_off, &corrupt_ent_size); + } else if (corrupt_level == 2){ + get_psp_entry(&flash, pspl2b_dir, corrupt_entryid, &backup_ent_off, &backup_ent_size); + get_psp_entry(&flash, pspl2a_dir, corrupt_entryid, &corrupt_ent_off, &corrupt_ent_size); + } else { + printk(BIOS_DEBUG, "not covered\n"); + } + corrupt_ent_off &= ~(flash_sector_size - 1); /* align down */ + corrupt_ent_size = ALIGN_UP(corrupt_ent_size, flash_sector_size); + printk(BIOS_DEBUG, "2a.1:corrupt_ent_off=%x, corrupt_ent_size=%x\n", corrupt_ent_off, corrupt_ent_size); + spi_flash_erase(&flash, corrupt_ent_off, corrupt_ent_size); + backup_ent_off &= ~(flash_sector_size - 1); + backup_ent_size = ALIGN_UP(backup_ent_size, flash_sector_size); + printk(BIOS_DEBUG, "2b.1:back_ent_off=%x, back_ent_size=%x\n", backup_ent_off, backup_ent_size); + for (index=0; index<corrupt_ent_size; index += flash_sector_size) { + printk(BIOS_DEBUG, "index=%x\n", index); + spi_flash_read(&flash, backup_ent_off + index, flash_sector_size, data); + spi_flash_write(&flash, corrupt_ent_off + index, flash_sector_size, data); + } + do_cold_reset(); + for (;;); +} diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h index 1506420..6d54c34 100644 --- a/src/soc/amd/cezanne/include/soc/cpu.h +++ b/src/soc/amd/cezanne/include/soc/cpu.h @@ -9,4 +9,6 @@ #define CEZANNE_VBIOS_VID_DID 0x10021638 #define BARCELO_VBIOS_VID_DID 0x100215e7 +void abrecovery(void); + #endif /* AMD_CEZANNE_CPU_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2cdab00a7122e4831fe5d91cf5d390ad11db0999 Gerrit-Change-Number: 84577 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/common: Add function to check the if it is in A/B recovery
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

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[S] Change in coreboot[main]: amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84440?usp=email to look at the new patch set (#3). Change subject: amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery ...................................................................... amdfwtool: Reorder the PSP L2 and BIOS L2 for A/B recovery For A/B recovery, it is better, even though it is not mandatory, to put BIOS level 2 table next to its PSP level2. So the relative addresses of BIOS table are the same. So all the data in B could be a copy of A. Identical binary test on all non A/B recovery platform. Booting test on Majolica with A/B recovery enabled. Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/84440/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia25277d307329a2fa66d38d1a7fc21b18246cfe6 Gerrit-Change-Number: 84440 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Move ISH before PSP L2
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Bao Zheng, Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84533?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: amdfwtool: Move ISH before PSP L2 ...................................................................... amdfwtool: Move ISH before PSP L2 It is more reasonable. Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84533/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Gerrit-Change-Number: 84533 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Add function to check AB recovery
by Bao Zheng (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Bao Zheng, Zheng Bao. Hello Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84534?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: amdfwtool: Add function to check AB recovery ...................................................................... amdfwtool: Add function to check AB recovery Change-Id: I491d106bac94698419cbb5ec269e51421250e3a6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/84534/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I491d106bac94698419cbb5ec269e51421250e3a6 Gerrit-Change-Number: 84534 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Revise IIO domain ACPI name encoding
by Patrick Rudolph (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84310?usp=email ) Change subject: soc/intel/xeon_sp: Revise IIO domain ACPI name encoding ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7 Gerrit-Change-Number: 84310 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 28 Sep 2024 04:51:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/lint: Use bigint for hexadecimal values in handle_range
by Subrata Banik (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Martin L Roth. Hello Karthik Ramasubramanian, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84575?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/lint: Use bigint for hexadecimal values in handle_range ...................................................................... util/lint: Use bigint for hexadecimal values in handle_range The `handle_range` function in `kconfig_lint` was failing to correctly handle large hexadecimal values ( 64-bit value) due to limitations with Perl's handling of standard integers. This commit modifies the function to use the `bigint` pragma, enabling it to handle arbitrarily large integers. This prevents issues with 64-bit hexadecimal values and ensures accurate comparisons for range validation. Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M util/lint/kconfig_lint 1 file changed, 16 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84575/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674 Gerrit-Change-Number: 84575 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Deprecate SoC-specific global reset status configs
by Subrata Banik (Code Review) 28 Sep '24

28 Sep '24

Attention is currently required from: Andrey Petrov, Christian Walter, David Hendricks, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Lean Sheng Tan, Nick Vaccaro, Nico Huber, Pranava Y N, Ronak Kanabar, Sean Rhodes, Tarun, Werner Zeh. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84572?usp=email ) Change subject: soc/intel: Deprecate SoC-specific global reset status configs ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/84572/comment/0efbc990_40ae4bc0?us… : PS4, Line 346: depends on SOC_INTEL_COMMON_FSP_RESET > Acknowledged I ran into the below issue with range handling 64-bit value ``` Argument "0x40000003" isn't numeric in numeric ne (!=) at util/lint/kconfig_lint line 872. Argument "0x4000000000000003" isn't numeric in numeric ne (!=) at util/lint/kconfig_lint line 872. Argument "0x40000008" isn't numeric in numeric ne (!=) at util/lint/kconfig_lint line 872. Argument "0x4000000000000008" isn't numeric in numeric ne (!=) at util/lint/kconfig_lint line 872. ``` submitted https://review.coreboot.org/c/coreboot/+/84575/1 for adding 64-bit value support. Please let me know your thoughts. -- To view, visit https://review.coreboot.org/c/coreboot/+/84572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f Gerrit-Change-Number: 84572 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 28 Sep 2024 03:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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