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Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 10:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/be82d030_d85cb561?us… :
PS9, Line 129: #pragma pack (pop)
> Please update either syntax in all files, which will help in maintaining consistency across the modu […]
Acknowledged
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83692?usp=email )
Change subject: mb/supermicro/x10slm-f: Add board id for flashing via BMC
......................................................................
mb/supermicro/x10slm-f: Add board id for flashing via BMC
The ID for X10SLM+F is 0811 as reported by Knogle on IRC.
Change-Id: Ie58aad50e66efbc3113541884beea9668d886b5d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83692
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/supermicro/x10slm-f/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Felix Held: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig
index 28c7c1a..212fc90 100644
--- a/src/mainboard/supermicro/x10slm-f/Kconfig
+++ b/src/mainboard/supermicro/x10slm-f/Kconfig
@@ -28,4 +28,8 @@
config ENABLE_DDR_2X_REFRESH
default y
+config SUPERMICRO_BOARDID
+ string
+ default "0811"
+
endif
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Change subject: mb/supermicro/x10slm-f: Add board id for flashing via BMC
......................................................................
Patch Set 1: Code-Review+2
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Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#46).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,273 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/46
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Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 45:
(2 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/1e8406c9_f5a5a55f?us… :
PS36, Line 133: 10
> Hi, as per EDS v0.7 #815002, chapter 21.0, support for up
> to 8 USB 2.0.
> I am not able to find the doc "731941".
8 is for PTL-P I believe for PTL-U, it's 6 if i'm not wrong as per Intel doc.
For now, keep 8 as we aee going to work on PTL-UH (P).
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/1dae2d57_2bb7084a?us… :
PS32, Line 19: #define SAF_BASE_ADDRESS 0xfa000000
> Hi Subrata, due to document v1.1 is not released externally yet, i am working with Intel internal team to make it sharebale over corsbug. Meanwhile, can we add "TO-DO" comment to the SAF Addr, and unblock this patch?
I don't understand what you mean by unblocking this CL. I won't be able to merge any CL unless the upper layer mainboard CL is V+1. Please continue adding other CLs and hopefully this doc reaches me in time.
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Ashish Kumar Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 9:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/b078ebb1_03d58242?us… :
PS9, Line 129: #pragma pack (pop)
> based on above reply, let me know if it is required to change from "#pragma (push , 1)" -> "#pragma […]
Please update either syntax in all files, which will help in maintaining consistency across the module.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83616?usp=email )
Change subject: util/cbfstool/common.h Fix wrong return value doc
......................................................................
util/cbfstool/common.h Fix wrong return value doc
The compressing and decompressing functions return 0 on success and not
the other way around.
Change-Id: I9f8653aa805c62eb4bfc3560d7880921830c2c59
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83616
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/cbfstool/common.h
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Elyes Haouas: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index 498aae6..88d5238 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -148,14 +148,14 @@
/* Compress in_len bytes from in, storing the result at out, returning the
* resulting length in out_len.
- * Returns 0 on error,
+ * Returns 0 on success,
* != 0 otherwise, depending on the compressing function.
*/
typedef int (*comp_func_ptr) (char *in, int in_len, char *out, int *out_len);
/* Decompress in_len bytes from in, storing the result at out, up to out_len
* bytes.
- * Returns 0 on error,
+ * Returns 0 on success,
* != 0 otherwise, depending on the decompressing function.
*/
typedef int (*decomp_func_ptr) (char *in, int in_len, char *out, int out_len,
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