coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: move UGOP_ESOL config to FSP
by Jayvik Desai (Code Review) 05 Aug '24

05 Aug '24

Jayvik Desai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83769?usp=email ) Change subject: move UGOP_ESOL config to FSP ...................................................................... move UGOP_ESOL config to FSP This patch moves the Metorlake early sign of life config out of the SOC-specific config and into the FSP driver config. BUG=NA TEST=Able to build google/rex and checked the config in output. Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83769/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 9ea1526..715d7ed 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -457,6 +457,15 @@ This option allows to create `Debug Event Handler` to print FSP debug messages to output device using coreboot native implementation. +config FSP_UGOP_EARLY_SIGN_OF_LIFE + bool + default n + help + Enable the FSP-M Sign-of-Life feature to display a + configurable text message on screen during memory training + and CSME update. + + config DISPLAY_FSP_TIMESTAMPS bool "Display FSP Timestamps" default n diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index ec8c318..274cabf 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -21,6 +21,8 @@ select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_USES_CB_DEBUG_EVENT_HANDLER + select FSP_UGOP_EARLY_SIGN_OF_LIFE if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON + select VBT_CBFS_COMPRESSION_DEFAULT_LZ4 if FSP_UGOP_EARLY_SIGN_OF_LIFE select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP @@ -457,16 +459,6 @@ help slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Meteor Lake. -config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE - bool - default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON - depends on MAINBOARD_HAS_CHROMEOS - select VBT_CBFS_COMPRESSION_DEFAULT_LZ4 - help - Enable the FSP-M Sign-of-Life feature to display a - configurable text message on screen during memory training - and CSME update. - config SOC_PHYSICAL_ADDRESS_WIDTH int default 42 diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec78383..4018ee8 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -511,7 +511,7 @@ soc_memory_init_params(m_cfg, config); - if (CONFIG(SOC_INTEL_METEORLAKE_SIGN_OF_LIFE)) + if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE)) fill_fspm_sign_of_life(m_cfg, arch_upd); mainboard_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/83769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd Gerrit-Change-Number: 83769 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, Sumeet R Pawnikar. Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 14: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82682/comment/46bdff6b_7ceb0d4a?us… : PS11, Line 12: hard code to > is hard coded to Done https://review.coreboot.org/c/coreboot/+/82682/comment/5bbce515_d43bc9e2?us… : PS11, Line 12: 27000(27A) > Please add a space before the (. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Aug 2024 15:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, Sumeet R Pawnikar. Simon Yang has posted comments on this change by Simon Yang. ( https://review.coreboot.org/c/coreboot/+/82682?usp=email ) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... Patch Set 14: (5 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/82682/comment/23bc4a99_be6d2c61?us… : PS11, Line 782: ONLY > only Done https://review.coreboot.org/c/coreboot/+/82682/comment/afc625a8_df098d96?us… : PS11, Line 783: Default is set to 27000(27A) > Defaults to … Done https://review.coreboot.org/c/coreboot/+/82682/comment/9b3bcd9b_15cb410d?us… : PS11, Line 783: 27000(27A) > Please add a space before the (. Done https://review.coreboot.org/c/coreboot/+/82682/comment/bfb2ad28_45f7f083?us… : PS11, Line 784: Range > *Allowed values* or something similar? change to *Recommended value*? https://review.coreboot.org/c/coreboot/+/82682/comment/64f5665f_aa2191b3?us… : PS11, Line 786: uint16_t vccin_aux_imon_iccmax > Could it be made an enum? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Aug 2024 15:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82682?usp=email to look at the new patch set (#14). Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and add a printk to output a debug message to observe whether the value is changing as expected. Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek/common: Refactor EINT driver
by Yu-Ping Wu (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xi Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/83703?usp=email ) Change subject: soc/mediatek/common: Refactor EINT driver ...................................................................... Patch Set 2: (2 comments) File src/soc/mediatek/common/include/soc/gpio_common.h: https://review.coreboot.org/c/coreboot/+/83703/comment/668ebf2b_bd598adf?us… : PS2, Line 123: void struct eint_regs https://review.coreboot.org/c/coreboot/+/83703/comment/e1e03199_eb43da79?us… : PS2, Line 122: void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit); : void *eint_find_reg_addr(gpio_t gpio); Since these functions are still declared here in gpio_common.h and are related to gpio, how about: 1. Rename eint_v1.c to gpio_eint_v1.c 2. Use `gpio_` prefix for these 2 functions (for example `gpio_get_eint_reg` and `gpio_calc_eint_pos_bit`) -- To view, visit https://review.coreboot.org/c/coreboot/+/83703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie53abc23971bfa39250ebd7dd48e28d6b91c5973 Gerrit-Change-Number: 83703 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 05 Aug 2024 15:46:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83635?usp=email to look at the new patch set (#45). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/chip.h A src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/include/soc/gpe.h A src/soc/intel/pantherlake/include/soc/meminit.h A src/soc/intel/pantherlake/include/soc/msr.h A src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/romstage.h A src/soc/intel/pantherlake/include/soc/soc_chip.h A src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/meminit.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/reset.c A src/soc/intel/pantherlake/romstage/Makefile.mk A src/soc/intel/pantherlake/romstage/fsp_params.c A src/soc/intel/pantherlake/romstage/romstage.c A src/soc/intel/pantherlake/romstage/systemagent.c 18 files changed, 1,367 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 45 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Subrata Banik (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... Patch Set 43: (2 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83635/comment/3983cdfd_79478559?us… : PS43, Line 41: help : Intel Pantherlake support. Mainboards should specify the SoC : type using the `SOC_INTEL_PANTHERLAKE_*` options instead : of selecting this option directly. : Can't you move into the base CL that introduces SOC_INTEL_PANTHERLAKE_BASE? https://review.coreboot.org/c/coreboot/+/83635/comment/cf30f6e7_06d790c9?us… : PS43, Line 170: # Baudrate = (UART source clock * M) /(N *16) : # PTL UART source clock: 120MHz why diff? -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 43 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 05 Aug 2024 15:37:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa: Add Vccin Aux Imon Iccmax default value for nissa/trulo
by Simon Yang (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83725?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik, Code-Review+2 by Sumeet R Pawnikar, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/nissa: Add Vccin Aux Imon Iccmax default value for nissa/trulo ...................................................................... mb/google/nissa: Add Vccin Aux Imon Iccmax default value for nissa/trulo Add default value in nissa and trulo devicetree.cb, ODM have to review the board design to follow RDC#646929 Power Map requirement. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and confirm the value changed Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83725/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c Gerrit-Change-Number: 83725 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
by Simon Yang (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Simon Yang, Subrata Banik, Sumeet R Pawnikar. Hello Daniel Peng, Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82682?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting ...................................................................... soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting According to RDC#646929 Power Map, there are two expected values of VccInAuxImonIccImax and the value has to align with HW design. But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A), hence, provide a config for projects modification. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Modify the register and add a printk to output a debug message to observe whether the value is changing as expected. Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82682/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/82682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657 Gerrit-Change-Number: 82682 Gerrit-PatchSet: 13 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 05 Aug '24

05 Aug '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra, Subrata Banik. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83635?usp=email to look at the new patch set (#44). Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/chip.h A src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/include/soc/gpe.h A src/soc/intel/pantherlake/include/soc/meminit.h A src/soc/intel/pantherlake/include/soc/msr.h A src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/romstage.h A src/soc/intel/pantherlake/include/soc/soc_chip.h A src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/meminit.c A src/soc/intel/pantherlake/p2sb.c A src/soc/intel/pantherlake/reset.c A src/soc/intel/pantherlake/romstage/Makefile.mk A src/soc/intel/pantherlake/romstage/fsp_params.c A src/soc/intel/pantherlake/romstage/romstage.c A src/soc/intel/pantherlake/romstage/systemagent.c 18 files changed, 1,367 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 44 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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