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Hello Bob Moragues, Jon Murphy, Nick Vaccaro, Sumeet R Pawnikar, build bot (Jenkins),
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Code-Review+1 by Bob Moragues, Code-Review+2 by Jon Murphy, Code-Review+2 by Sumeet R Pawnikar, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Tune Touchpad I2C parameters
......................................................................
mb/google/brox: Tune Touchpad I2C parameters
Adjust Touchpad I2C fall time configuration such that it meets the
I2C fast mode specification(<= 400KHz).
BUG=b:328670295
TEST=Build Brox firmware and boot to OS. Confirm the I2C bus
frequency(375 KHz), rise(650 ns) and fall(330 ns) times meet the
specification.
Change-Id: I0006bfb9bb5839ffa1248d9f2ea055160ed0936e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83755/2
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Change subject: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/blobs/+/83748/comment/d43f6a42_eddf40cb?usp=e… :
PS5, Line 9: readed
> read
Done
https://review.coreboot.org/c/blobs/+/83748/comment/2797545f_fa07db45?usp=e… :
PS5, Line 12: value(from full-k reference)
> Please add a space before (.
Done
https://review.coreboot.org/c/blobs/+/83748/comment/6325e760_d103f553?usp=e… :
PS5, Line 12: let
> make?
Done
https://review.coreboot.org/c/blobs/+/83748/comment/a595a3dc_96972060?usp=e… :
PS5, Line 9: For fast-k RX flow, Vref value is readed from the MRC_CACHE, but the
: preferred RX Vref value 0xE is set, with no re-calibration. But some
: DRAM vendor may use higher RX Vref value, increase the default RX
: Vref value(from full-k reference) to let different DRAM RX Vref
: compatible.
:
> Please make use of 72 characters per line.
Acknowledged
https://review.coreboot.org/c/blobs/+/83748/comment/cd074551_b450ff46?usp=e… :
PS5, Line 16: TEST=Check the fast-k RX Vref value is normal
> How? What DRAM vendor/model?
Done
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Attention is currently required from: Xixi Chen, Yidi Lin, Yu-Ping Wu.
Hello Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/blobs/+/83748?usp=email
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
......................................................................
soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
For fast-k RX flow, Vref value is read from the MRC_CACHE, but the
preferred RX Vref value 0xE is set, with no re-calibration. But some
DRAM vendor may use higher RX Vref value, increase the default RX Vref
value (from full-k reference) to make different DRAM RX Vref compatible.
BUG=b:352632973
TEST=Check the Nanya DRAM fast-k RX Vref value is normal
Logs:
[3732][CH0][RK0][RX] Best Vref B0 = 22, Window Min 25 at DQ5 ...
[3732][CH0][RK0][RX] Best Vref B1 = 22, Window Min 28 at DQ10 ...
The "Best Vref" value is the same to full-k Vref.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: Id7df502346d590d3cf3827f48d868da021f6ec9d
---
M soc/mediatek/mt8186/dram.elf
M soc/mediatek/mt8186/dram.elf.md5
M soc/mediatek/mt8186/dram_release_notes.txt
3 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/48/83748/6
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Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83671?usp=email )
Change subject: mb/google/trulo: support ISH
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/trulo/gpio.c:
https://review.coreboot.org/c/coreboot/+/83671/comment/9fa3247f_2798a470?us… :
PS2, Line 147: PAD_CFG_NF
> Let me change it to lock config and test. Will update the patch after test.
Can we resolve this ? As ISH Firmware needs GPIO to be not locked
Details updated in bug
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83607?usp=email )
Change subject: mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config
......................................................................
mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config
Match PCIe root port allocation and associated comments to
boardview, as follows:
Z77 PCIe ports 1-4: PCIEX16_3 (x4)
Z77 PCIe port 5: PCIEX1_1
Z77 PCIe port 6: RTL8111F LAN
Z77 PCIe port 7: ASM1042 USB3
Z77 PCIe port 8: ASM1061 eSATA
CPU PCIe lanes 1-8: PCIEX16_1
CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16
and PCIEX16_2 lanes 1-8
(CPU PCIe lanes are not covered by overridetree.cb.)
These are not hardware tested.
Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
1 file changed, 4 insertions(+), 7 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 4613c12..0483f4a 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -25,13 +25,10 @@
}"
device ref pcie_rp1 on end # PCIEX_16_3
- device ref pcie_rp2 on end # RTL8111F
- device ref pcie_rp3 off end
- device ref pcie_rp4 off end
- device ref pcie_rp5 off end
- device ref pcie_rp6 on end # ASM1042 USB3
- device ref pcie_rp7 on end # ASM1061 eSATA
- device ref pcie_rp8 off end
+ device ref pcie_rp5 on end # PCIEX1_1
+ device ref pcie_rp6 on end # RTL8111F
+ device ref pcie_rp7 on end # ASM1042 USB3
+ device ref pcie_rp8 on end # ASM1061 eSATA
device ref lpc on
chip superio/nuvoton/nct6779d
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Change subject: mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
i'm not 100% certain how the function numbers of the bridges are assigned on the intel systems, but this change seems to bring this board in line with the other variants. since Matt has +2ed it, i'll submit it
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Change subject: soc/amd/common/psp_smi_flash: validate target SPI region ID
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: soc/amd/common/psp_smi_flash: add command-specific data structures
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: soc/amd/common/psp: add and call PSP SMI SPI access function stubs
......................................................................
Patch Set 3:
This change is ready for review.
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